myRIO host vi to fpga vi communication

[Lahari]

Hello all. 

I am trying to send analog data from host vi to fpga vi (fpga target being myRIO- 1900), via read/write control from the 'FPGA interface' pallete. 

I observe that while the iteration number of while loop in host vi is still 0, the iteration number of the timed loop in fpga vi is 1,19,000 approximately. This could mean that between 'open reference vi' is being called and the iteration of while loop in host vi is completed, there is a huge time gap and the fpga vi is executing even before the analog data is actually being transferred from host vi to fpga vi. 

How do I resolve this issue? 

Kindly suggest. 

[DahlmanR]

Hello!

If you'd like to wait to start acquiring on the FPGA until the Real-Time code has had time to start up, you can utilize interrupts. Essentially, you can have the FPGA VI wait on an interrupt that is being sent from the Real-Time VI. Once it receives the interrupt, then have it proceed to start its main loop.

Synchronizing FPGA VIs and Host VIs Using Interrupts (FPGA Interface): https://www.ni.com/docs/en-US/bundle/labview-fpga-module/page/synchronizing-fpga-vis-and-host-vis-us...

It's also important to know that Read/Write Controls will only pass the latest data. If you'd like to pass every point of data, consider using FIFOs. 

Understanding Communication Options Between the Windows HMI, RT Processor, and FPGA: https://www.ni.com/en/support/documentation/supplemental/16/understanding-communication-options-betw...

Hope this helps!

R Dahlman

[Lahari]

Thank you for your response. 

I tried using FIFOs as per your suggestion. But even in that case, I find that the iteration number of the fpga vi is in no match to the iteration number of the host vi, although both are interdependent for data. I need that both the VIs execute as per their data dependency. But despite their data dependency, they are executing without any synchronisation and hence their iteration numbers are having a large difference. 

[DahlmanR]

Please take another closer read of my initial post. 

FIFOs are for ensuring every point of data is passed between the FPGA and the Real Time VI. You could use interrupts to synchronize your Real Time and FPGA VIs. Though you could try to use a DMA FIFO for a polling type synchronization, you would have to ensure you set them up correctly.

If you are having trouble understanding from the Help page I linked in the first post, there is a very simple example of using interrupts in the NI Example Finder as well (LabVIEW Help >> Find Examples >> Hardware Input and Output >> CompactRIO >> Fundamentals >> Host Synchronization >> Interrupts)

If you're not a fan of trying interrupts, there are a couple other options covered here: 
Synchronizing FPGA VIs and Host VIs Using Interrupts (FPGA Interface)    https://www.ni.com/docs/en-US/bundle/labview-fpga-module/page/synchronizing-fpga-vis-and-host-vis-us...

[Lahari]

Hello.

I got the results using FIFOs, thank you very much for the suggestion.

But the major problem now is the timing of the result. Where I achieved microseconds as the time of output in simulation mode of FPGA in myRIO, I am acheiving seconds as the time of output when myRIO is connected. I am very much unaware of why is this happening, why is the latency between host and FPGA program running in myRIO is so large as compared to what it was in simulation mode, 10^6 times.

And the host vi execution time on front panel shows 30s in less than 3 real seconds. So it is definitely not that the latency is due to actual delay in data transfer between the host vi and fpga vi. 

Please help me as to what can be the possible reasons for this.