plz have a look here

[vikas.singh]

actually i want to know how the cRIO hardwares attached to real time controller and how it will manage nothing is given about the connection and to test the specification of perticular cRIO....

[preston_johnson]

Here is a good link with an overview of the cRIO architecture:

http://zone.ni.com/devzone/conceptd.nsf/webmain/925A7C29B99BE5C286256EE40079F0B8

The FPGA backplane (where the modules are) connects to the RT controller via a PCI bus.  There are interrupt, polling, and DMA schemas for data transfers, signaling and related communications between the FPGA LabVIEW code and the RT LabVIEW code.