10-23-2021 07:20 AM
Hi,
the user manual states that the 5V output can provide 1.5A and the FPGA_VIO and 3.3V_AUX are each given as 0.33 A. Does that mean that they can provide 0.66 A together but each one of them can only provide 0.33 A or does it mean that they can provide 0.33 A together where each one of them can be loaded up to the full amount ?
Will the load on one of the 3.3 V rails affect the regulation of the other ?
11-05-2021
06:44 AM
- last edited on
08-21-2025
05:28 PM
by
Content Cleaner
Hello,
According to the datasheet (see screenshot below) each of them can deliver up to 0.33 A current each. But keep in mind that this is the sum of the current of the FPGA_VIO or 3.3V_AUX port pins.
If you wish you can describe what you are looking for, or planning to do.
11-05-2021 07:17 AM
Dear VA.KI,
thanks for replying. I know this table ( I quoted the values in my questions).
Why do you believe that 0.33A is the sum of the current deliverable from the FPGA_VIO and 3.3V_AUX ports ? I.e. if I draw 0.2 A from FPGA_VIO, I would be only able to draw 0.13 A (safely) from 3.3V_AUX? How do you infer this from the table ? I believe it is ambiguous.
I am planning to use these rails to supply a couple of groups on my board. The total consumption of current from the 3.3 V supply could exceed 0.33 A (but will be below 0.66 A).
11-05-2021
08:26 AM
- last edited on
08-21-2025
05:29 PM
by
Content Cleaner
11-05-2021 08:41 AM
Dear VA.KI,
thank you again for providing further links. Unfortunately none of the material answers my question.
Could you please be so kind and quote the exact phrase that you believe tells unambiguously that the combined total current to be drawn from FPGA_VIO and 3.3V_AUX is 0.33 A and not 0.66 A?
11-09-2021 01:45 AM
Hello toby,
Sorry, probably I wasn't clear.
In sum, the current should be 0.66 A by meaning 0.33 A for each FPGA_VIO and 3.3V_AUX.
Mabe my first reply confused you. There I meant the following: if there are multiple FPGA_VIO or 3.3V_AUX pins (I mean physical pins) then the current of 0.33 A is for all FPGA_VIO or 3.3V_AUX pins combined.