Delay with DRAM - PXI 5644 R

[mourad_FAKHFAKH]

Hello , 

I have an input RF signal to which i want to apply a variable delay that goes to 200 ms with a precision of 10 ns . For this i'm planning to use the RAM memory by writing the I,Q data and reading it depending on the value of the Delay (Value received from host ) . Working at 120 MHz and using the DRAM of the PXI 5644 (512 MB) , it is theorically possible to apply a delay of 200 ms . I have already explored the MIMO channel emulation example in which a delay was applied to the signal . In this example , I,Q data was stored in the BRAM . In my case the BRAM can't contain enough data to delay the signal of 200 ms, DRAM is the only possible way to apply this delay .So my concerns are about the non determinism of the DRAM acces , how can i manage the DRAM access so that i can apply an accurate delay to my signal ? Is there an example in LabVIEW that implements a deterministic access to the DRAM ? 

Thank you for your help .

[David-A]

DRAM may not be deterministic but BRAM is. So buffer the input and output of the DRAM with a BRAM buffer sufficiently large enough to smooth out any of the non-deterministic wrinkles that the DRAM may have. 

[mourad_FAKHFAKH]

Thank you for your response David-A  , 

Buffering the input and the output seems to be a solution to my problem .However,  i have some questions in relation to this access mode .

1- How can i arbitrate the read/write commands for the DRAM and being sure that no latency will be caused at any time ?

2- Since the PXI 5644 R datasheet doesn't indicate the access time of the DRAM , how can i choose the right clock domain for the DRAM and the FIFO's length in order prevent Overflows/Underflows ? 

Thanks for any comment . 

[David-A]

What version of labview are you using? If you're using 2014 and don't mind installing another driver there is some DRAM FIFO example code that you could use.

Not sure what the ideal clock domain for the dram on the 5644r is though, or the data width of the dram.