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Do I need to Close FPGA reference in the sample project? (Need help on modifying USRP sample project)

I am experimenting on the sample project of LabVIEW, entitled "Tx and Rx Streaming time". I edited the Open Device.vi host vi and  replaced the block named "Open Dynamic Bitfile Reference" with the "Open FPGA VI Reference" block. (Which is shown in the attached image). Now, I read some sources that I need to call the "Close FPGA VI Reference" block everytime I open it, the problem is when I call it, it crashes (or close entirely) the LabVIEW. My question is, Do I really need to call the "Close FPGA" block? If so, can someone teach me where and how to properly call it? Thanks in advance. 

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Hi VDN1,

 

Before diving too deep into the technicalities of calling the USRP FPGA file, can you help us understand why you want to modify the code to call the FPGA this way? What are you hoping to get out of this modification?

Chase
NI Technical Support Engineer
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