I am trying to run the benchmark_rate utility on the x440 with 2 TX channels at a 125 MHz sample/master clock rate, but cannot get it to work properly. It seems UHD times out while configuring the x440. I have tried this using both the CG_400 and CG_1600 images and saw the same error. The strange thing is it works perfectly fine using a 250 MHz master clock rate. My understanding is that a 125 MHz master clock rate is supported by both of these images. Below is the terminal output from the benchamark_rate utility at 125 MHz:
sudo ./benchmark_rate --tx_rate 125e6 --tx_subdev "A:0 B:0" --tx_channels 0,1 --args "addr=192.168.20.2,mgmt_addr=192.168.1.123,master_clock_rate=125e6,use_dpdk=1"
[INFO] [UHD] linux; GNU C++ version 13.3.0; Boost_108300; DPDK_23.11; UHD_4.8.0.main-0-81dac6ce
EAL: Detected CPU lcores: 32
EAL: Detected NUMA nodes: 1
EAL: Detected shared linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/rte/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: Probe PCI driver: mlx5_pci (15b3:1017) device: 0000:07:00.0 (socket -1)
TELEMETRY: No legacy callbacks, legacy socket not created
[00:00:00.000241] Creating the usrp device with: addr=192.168.20.2,mgmt_addr=192.168.1.123,master_clock_rate=125e6,use_dpdk=1...
[INFO] [MPMD] Initializing 1 device(s) in parallel with args: mgmt_addr=192.168.1.123,type=x4xx,product=x440,serial=33B79AE,name=ni-x4xx-33B79AE,fpga=CG_1600,claimed=False,addr=192.168.20.2,master_clock_rate=125e6,use_dpdk=1
[INFO] [MPMD] Rebooting MPM before device initialization!
[INFO] [MPM.PeriphManager] init() called with device args `fpga=CG_1600,master_clock_rate=(125000000.0, 125000000.0),mgmt_addr=192.168.1.123,name=ni-x4xx-33B79AE,product=x440,use_dpdk=1,clock_source=internal,time_source=internal,initializing=True'.
[INFO] [MPM.RPCServer] Resetting peripheral manager.
[INFO] [MPM.PeriphManager] Device serial number: 338A4C8
[INFO] [MPM.PeriphManager.Clk_Policy] Bypassing RFDC PLL
[INFO] [MPM.PeriphManager.Clk_Policy] Bypassing RFDC PLL
[INFO] [MPM.PeriphManager.Clk_Policy] Bypassing RFDC PLL
[INFO] [MPM.PeriphManager.ClkMgr] Using Clock Configuration:
DB0: Master Clock Rate: 368.64 MSps @Converter Rate 2.94912 GHz
DB1: Master Clock Rate: 368.64 MSps @Converter Rate 2.94912 GHz
[INFO] [MPM.PeriphManager] Initialized 2 daughterboard(s).
[INFO] [MPM.PeriphManager] init() called with device args `boot_init=True,clock_source=internal,time_source=internal,initializing=True'.
[INFO] [MPM.PeriphManager.Clk_Policy] Using RFDC PLL
[INFO] [MPM.PeriphManager.Clk_Policy] Bypassing RFDC PLL
[INFO] [MPM.PeriphManager.ClkMgr] Using Clock Configuration:
DB0: Master Clock Rate: 125.0 MSps @Converter Rate 1.0 GHz
DB1: Master Clock Rate: 125.0 MSps @Converter Rate 1.0 GHz
[INFO] [MPM.PeriphManager] init() called with device args `fpga=CG_1600,master_clock_rate=(125000000.0, 125000000.0),mgmt_addr=192.168.1.123,name=ni-x4xx-33B79AE,product=x440,use_dpdk=1,clock_source=internal,time_source=internal,initializing=True'.
[INFO] [0/Radio#0] Clocking reconfigured, running ADC Self Cal on DB0...
[INFO] [0/Radio#0] Calibrated 1 channels.
[ERROR] [RFNOC::GRAPH] Error during initialization of block 0/Radio#1!
[ERROR] [RFNOC::GRAPH] Caught exception while initializing graph: RfnocError: OpTimeout: Control operation timed out waiting for space in command buffer
Error: RuntimeError: Failure to create rfnoc_graph.
If anyone could provide any information on why this is occuring, it would be greatly appreciated.
