USRP FPGA Recompile Error

[Wired_]

I am building my application based on Full Duplex Streaming as base.

After making some changes whenever I run the application it runs well for first time. But once I close the first run it returns below shown error on each of the successive attempts.

I am using USRP RIO 2952.

The System Designer View is as shown herein.

Is it due to device unsuccessfuly closed or application forces aborted?