06-30-2021 07:53 AM
I have an application running with an USRP 2945(MXI), LabVIEW 2019(64bit), USRP-driver 19.0.
I use it in the RIO mode and have several DMA data streams to the host where I receive the data with the acquire read region method. The hole application runs very reliably for days and weeks without problems.
When I update the USRP driver to 19.1,19.5, 20.0 or 20.5 I get an error after some data has been streamed:
I checked carefully any mistakes for the release data regions but there nothing I can spot.
So we decided to be stuck with the USRP-driver 19.0
Now we wanted to duplicate the system to increase our throughput and bought a new USRP 2945 device. But now I get this error message:
Therefore we need now to solve the error with the blocked read regions.
Is there anything known to have changed in the USRP driver from 19.0 to 19.1 that could explain the error and give a hint how to work around?
Has anyone else experienced a similar problem?
Is there a simple demo program that uses DMA with the acquire read region method that we can try out as an example to nail down the problem? otherwise I would have to write a minimal example to demonstrate the failure.
Any info, help or comment is welcome.
07-01-2021 06:31 AM
Hi,
Did you have a chance to update the USRP image after the driver update? Each driver has a specific FPGA image and updating it is mandatory.
Also, if the previous image was modified the new FPGA image modification is required as well.
Open the USRP utility and check the FPGA image. If an update is required - update it.
Hope this was useful.
07-07-2021 03:05 AM
I tried to update the image with the USRP utility. I get the following error message:
( I tried with USRO 19.0 first, then with USRP 20.5 installed. both time this error message)
Is there a newer USRP driver than 20.5 ?
By the way, in Package Manager, for USRP 20.5, there is a link:
that leads to nowhere:
Then I tried to update the firmware from MAX:
But it leads me to a directory with no usrp firmware:
I browsed to …/USRP/images/usrp_x310_fpga_HG.lvbitx and updated successfully the image:
I run my the software under LV 2020 SP1 and after some successful streaming of data (ca 30 sec) I get this error message as originally posted:
The same error when I open and run the software under LV 2019 SP1
Conclusion: updating the image of the FPGA on the device did not solve the problem nor did it change any behavior. It was very unlikely that the error is related to the image. The error happens on the host side of the dma streaming. Somehow the acquired read regions are not released. This is a software that runs nicely under USRP 19.0 but shows this error with USRP 19.1 and higher. This is critical bug that needs to be solved. What has changed in the driver from 19.0 to 19.1 that could explain this? is there a simple example with dma streaming to host using the acquire read region that proves it is working or shows the error?
in the meantime we could work with running the software under version 19.0. But we would need to downgrade the device firmware to 19.0 which we can't. So, can we exchange the usrp device to an older one?
07-07-2021 03:25 AM
The USRP utility shows that the FPGA image version is higher than the driver version.
it is possible to check with basic commands:
After the Image update, you need to turn off/on the USRP after which restarts the PC.
07-07-2021 05:13 AM
I did what you explained. here is the output:
C:\Program Files (x86)\National Instruments\NI-USRP\utilities>uhd_usrp_probe
_____________________________________________________
/
| Device: X-Series Device
| _____________________________________________________
| /
| | Mboard: X310
| | revision: 11
| | revision_compat: 7
| | product: 30959
| | mac-addr0: 00:80:2f:31:aa:1a
| | mac-addr1: 00:80:2f:31:aa:1b
| | gateway: 192.168.10.1
| | ip-addr0: 192.168.10.2
| | subnet0: 255.255.255.0
| | ip-addr1: 192.168.20.2
| | subnet1: 255.255.255.0
| | ip-addr2: 192.168.30.2
| | subnet2: 255.255.255.0
| | ip-addr3: 192.168.40.2
| | subnet3: 255.255.255.0
| | serial: 31FA23D
| | FW Version: 6.0
| | FPGA Version: 38.0
| | FPGA git hash: be53058
| |
| | Time sources: internal, external, gpsdo
| | Clock sources: internal, external, gpsdo
| | Sensors: ref_locked
| _____________________________________________________
| /
| | RFNoC blocks on this device:
| |
| | * 0/DDC#0
| | * 0/DDC#1
| | * 0/DUC#0
| | * 0/DUC#1
| | * 0/Radio#0
| | * 0/Radio#1
| | * 0/Replay#0
| _____________________________________________________
| /
| | Static connections on this device:
| |
| | * 0/SEP#0:0==>0/DUC#0:0
| | * 0/DUC#0:0==>0/Radio#0:0
| | * 0/Radio#0:0==>0/DDC#0:0
| | * 0/DDC#0:0==>0/SEP#0:0
| | * 0/Radio#0:1==>0/DDC#0:1
| | * 0/DDC#0:1==>0/SEP#1:0
| | * 0/SEP#2:0==>0/DUC#1:0
| | * 0/DUC#1:0==>0/Radio#1:0
| | * 0/Radio#1:0==>0/DDC#1:0
| | * 0/DDC#1:0==>0/SEP#2:0
| | * 0/Radio#1:1==>0/DDC#1:1
| | * 0/DDC#1:1==>0/SEP#3:0
| | * 0/SEP#4:0==>0/Replay#0:0
| | * 0/Replay#0:0==>0/SEP#4:0
| | * 0/SEP#5:0==>0/Replay#0:1
| | * 0/Replay#0:1==>0/SEP#5:0
| _____________________________________________________
| /
| | TX Dboard: dboard
| | ID: Unknown (0x0094)
| | Serial: 31DDBD8
| | _____________________________________________________
| | /
| | | TX Frontend: 0
| | | Name: Unknown (0x0094) - 0
| | | Antennas:
| | | Sensors:
| | | Freq range: 0.000 to 0.000 MHz
| | | Gain Elements: None
| | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz
| | | Connection Type: IQ
| | | Uses LO offset: No
| _____________________________________________________
| /
| | RX Dboard: dboard
| | ID: TwinRX Rev C (0x0095)
| | Serial: 31DDBD8
| | _____________________________________________________
| | /
| | | RX Frontend: 0
| | | Name: TwinRX RX0
| | | Antennas: RX1, RX2
| | | Sensors: lo_locked
| | | Freq range: 10.000 to 6000.000 MHz
| | | Gain range all: 0.0 to 93.0 step 1.0 dB
| | | Bandwidth range: 80000000.0 to 80000000.0 step 0.0 Hz
| | | Connection Type: II
| | | Uses LO offset: No
| | _____________________________________________________
| | /
| | | RX Frontend: 1
| | | Name: TwinRX RX1
| | | Antennas: RX1, RX2
| | | Sensors: lo_locked
| | | Freq range: 10.000 to 6000.000 MHz
| | | Gain range all: 0.0 to 93.0 step 1.0 dB
| | | Bandwidth range: 80000000.0 to 80000000.0 step 0.0 Hz
| | | Connection Type: QQ
| | | Uses LO offset: No
| _____________________________________________________
| /
| | TX Dboard: dboard
| | ID: Unknown (0x0094)
| | Serial: 31E086D
| | _____________________________________________________
| | /
| | | TX Frontend: 0
| | | Name: Unknown (0x0094) - 0
| | | Antennas:
| | | Sensors:
| | | Freq range: 0.000 to 0.000 MHz
| | | Gain Elements: None
| | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz
| | | Connection Type: IQ
| | | Uses LO offset: No
| _____________________________________________________
| /
| | RX Dboard: dboard
| | ID: TwinRX Rev C (0x0095)
| | Serial: 31E086D
| | _____________________________________________________
| | /
| | | RX Frontend: 0
| | | Name: TwinRX RX0
| | | Antennas: RX1, RX2
| | | Sensors: lo_locked
| | | Freq range: 10.000 to 6000.000 MHz
| | | Gain range all: 0.0 to 93.0 step 1.0 dB
| | | Bandwidth range: 80000000.0 to 80000000.0 step 0.0 Hz
| | | Connection Type: II
| | | Uses LO offset: No
| | _____________________________________________________
| | /
| | | RX Frontend: 1
| | | Name: TwinRX RX1
| | | Antennas: RX1, RX2
| | | Sensors: lo_locked
| | | Freq range: 10.000 to 6000.000 MHz
| | | Gain range all: 0.0 to 93.0 step 1.0 dB
| | | Bandwidth range: 80000000.0 to 80000000.0 step 0.0 Hz
| | | Connection Type: QQ
| | | Uses LO offset: No
what should I do now?
07-07-2021 06:27 AM
this shows that the FPGA image is working correctly. What about the outcome of the uhd_find_devices command?
07-08-2021 08:44 AM
unfortunately i can only post every 24h. But here the result of the uhd_find_devices command:
c:\Program Files (x86)\National Instruments\NI-USRP\utilities>uhd_find_devices
--------------------------------------------------
-- UHD Device 0
--------------------------------------------------
Device Address:
serial: 31FA23D
fpga: HG
name:
product: X310
resource: RIO0
type: x300
07-09-2021 06:08 AM
Hi,
No worries about response time. I would like to suggest trying once again to update the firmware. The image and the USRP are working correctly.
Please update the FPGA image only with the USRP utility.
07-12-2021 02:41 AM
ok I tryed it again:
USRP 20.5 was insatlled:
The USRP update utility finds correctly the device:
(note, it says rev 12!)
trying to write the image:
07-14-2021 08:36 AM
Please check USRP EEPROM:
The default location for the utilities is
C:\Program Files (x86)\National Instruments\LabVIEW 2015\vi.lib\LabVIEW Targets\FPGA\USRP\niusrprio_tools.llb
Note - edit path accordingly if you have a different version of LabVIEW and/or you have installed the x64 version
Use the initialize Examine Flash.vi and share the response in this conversation.