‎12-12-2017 04:23 AM
‎12-12-2017 08:43 AM
Are you trying to do this on the host? By that are you getting data from the USRP, processing the response in desktop LabVIEW, and sending it back to the USRP? You will never be able to get your response time into the microseconds without editing the code in the FPGA.
What sample rate is this running at? Just using NI's DSP blocks (on the FPGA) to correct the signals and adjust the sample rate will take close to 1.5us. You will have to add your processing on top of this.
Andy
‎12-17-2017 11:09 PM - edited ‎12-17-2017 11:11 PM
Thanks to u, Andy
On transmission side my sample rate is 6.6 M. and On reception its 11.11 M.
And yes my system is host. Now i come to know that i have to edit the code in the FPGA.
I have two Qs's.
1) Is there some VI's to get start with labview FPGA to build my own code for Tx (transmision) and Rx (Reception) . . . .
2) Upon Reception i have to wait (in micro seconds) and then transmit data . . . And this wait (in micro seconds) information is coming from Host . . .
May ALLAH rewards in advancve . . .
‎12-17-2017 11:10 PM - edited ‎12-17-2017 11:13 PM
AL
‎12-18-2017 08:30 AM
Obviously it goes without saying that you need to have the LV-FPGA module installed. If you don't have that you will need to install it and then probably reinstall USRP to make sure you get have all the proper files. The so already you will need to use the sample project for the USRP to get a good starting point. From the LabVIEW splash screen select File | New Project... Under the sample projects you will see NI-USRP. Select NI-USRP Simple Streaming. It will ask you for a folder and a prefix then will create your own private copy of the sample projected. You can modify any VI whose file name begins with the prefix that you specified.
If you haven't done much FPGA coding before, modifying the code might not be as easy and straight-forward as you would want. The basic idea is to replace the DMA FIFOs (Tx/Rx Stream 0/1) with local FIFOs. This would give you access to the Rx data for you to analyze for pulses and a FIFO to push Tx data for you to send output pulses.
Hopefully this gets you started down the right path.
‎12-18-2017 10:53 PM
Thanks . . . Brother Andy for your time.
Yes i worked on sample project before. Could it be Possible to receive data and then transmit its response (After analising Rx data) in micro seconds . . .?
(The basic idea is to replace the DMA FIFOs (Tx/Rx Stream 0/1) with local FIFOs. This would give you access to the Rx data for you to analyze for pulses and a FIFO to push Tx data for you to send output pulses.)
Any help about above as i am new to FPGA's . . .
Could i have that merged(Tx/Rx) VI.
‎12-19-2017 08:42 AM
I don't have all the necessary benchmarks handy but getting a response in under 10us is very possible. More than likely it will be under 5us.
Other than that I don't know exactly what you are asking for. I'm guessing the biggest effort will be implementing your code that looks for the pulses onto the FPGA. Not knowing much about your application I'm assuming you code will replace the Rx DMA FIFO with a local one. The Rx block will push data into that block at your 11.11MS/sec rate. You custom module will read from the FIFO and perform the analysis. When a pulse is found it will generate the Tx response (I'm assuming from a LUT) and supply a Tx local FIFO with 6.6MS/sec data.
As mentioned, all of this should happen in under 10us. If you are wanting an exact response time that will get a little more difficult but it is possible with some calibration.
Good luck.
‎12-20-2017 12:48 AM
Thanks Andy . . .
Do u have any experience of the following . . .
(When a pulse is found it will generate the Tx response (I'm assuming from a LUT) and supply a Tx local FIFO with 6.6MS/sec data.)
I just want to Start Rx (receive) data and check data Continuously if Rx (received) is a pulse. Tx (Transmision) starts.
If yes Could i have the VI which on Rx (Reception) of data start Tx (Transmision).
‎12-20-2017 09:49 AM
I don't have a VI that I can supply you because this part is very specific to your application. According to your first post you are doing pulse detection on the host. You would need to determine what that algorithm is and then implement it on the FPGA. You mentioned that you are new to FPGA so I would warn you there might be difficulties getting through the entire process:
I can provide you some advice via the forums but as you can see there is a lot that needs to be accomplished.
Most pulse detection algorithms have three basic parts:
Hope this helps.
Andy