usrp x440 bitfile creation of X4_200 image result in timing error

[usrpLover1]

Hello, 

for the past week im trying to create a new bitfile for the X440.

As a first step i successfully managed to create the X440_400 variants bitfile using the giving yamls.

While trying to recreate the  X4_200 image (without any changes) the implementation resulted in many timing errors, altough i tried using many implementation strategy.

this issue still occur when i strip all the duc and radio blocks.
 Is it a known issue? can i avoid it? am i doing something wrong?

  - ubuntu 22.04 

  - vivado 2021 with the patch

  - uhd 4.9.0

the command i used:

sudo -E rfnoc_image_builder -d x440 -y
/home/Desktop/workspace/uhd/fpga/usrp3/top/x400/x440_X4_200_rfnoc_image_core.yml
--save-project --GUI

[mikiofuku]

Hi
Here is a forum for LabVIEW USRP users.
You should post it to the USRP mailing list.

https://lists.ettus.com/list/usrp-users.lists.ettus.com

Regards,