Why is the DTACK* signal remaining in logic zero position with a successful RD/W

[bnl.gov]

I was curious to know why the waveform for DTACK* remained low when a successful Read and Write occurred.  In a VME manual, a pulse allowed the signal to be at logic 1 after completion but this never occured during my testing.  Also What makes DTACK* go high or low.  I am familiar with DTACK being asserted after a successful Read/Write, but was wondering if there were any other cases.

[TobyHex]

Hey BNL.gov,
Do you mind giving me a little more information on what type of VME controller you are using or two what manual you are referring to when you state, "In a VME manual." I was unsure by what you meant with that? Any further clarification on the type of hardware you are using can help me get you an answer asap. Thanks again and have a good day!
Regards,

Nicholas K

[TobyHex]

As well, I would like for you to take a look at the following article entitled, " Understanding the VXI/VME Interrupt and Signal Acknowledge Cycle," and let me know if it helps to answer your question! Thanks again.
Regards,

Nicholas K