Model step size

[Debz]

Hello,

I have a PXI-8106RT controller.

I'm trying to run a model (dll) created under Matlab. It's a voltage/current regulator. It's ok when the model is compiled with a 10kHz step size.

But when I go up to 100kHz the model is not running fine since the Model Count channel is dramatically increasing over the time.

I need to run the model at 10 MHz.

Is there a way to do this ? Do I have to set something under Matlab to get better performance? Do I need a better controller?

Thanks

[Jean-Philippe_C]

Hello,

Do you use your dll in LabVIEW or in Veristand?

Have look to this post. It may be useful for you:

http://forums.ni.com/t5/LabVIEW/Export-DLL-from-Matlab-and-import-in-Labview/m-p/1396490?requireLogi...

Regards

[Debz]

thanks for the advice but that's not what I wanted to know.

Let me clarify my question.

I'm generating a veristand dll with matlab. Then I'm deploying the dll on the real time controller using Veristand.

I have generated the same model with different step size. The 10kHz model is running fine since since the "Model Count" system channel of the controller is equal to 0 during the simulation. When I deploy the 100kHz model the Model Count channel keep increasing.

I would like to know if there is a way to increase the performance and have the model run properly at 100kHz.(some settings in matlab ? in Veristand ?)

If I update my controller to a Quad-core, will the performance be significantly better ? Which minimum step size could I expect?

[Devin_K]

Hi Debz,

There are two things you need to keep in mind here:

1) The rate at which your model is compiled at (step size)

2) The rate at which VeriStand is running on your system (configured on the Controller page in NI VeriStand)

In order to run your model in "real-time" (where 1 second of time in real life corresponds to one second of simulation), these two rates need to be equal (since VeriStand executes one time step of a model each iteration of its Primary Control Loop).  If this is your goal, a 10 MHz loop rate is not realistic, and will not be achievable with any real-time controller.  Even with our fastest controllers, it's generally not feasible to run VeriStand much faster than 10-15 kHz.

However, this real-time behavior may not actually be what you are after.  If you are only running model simulations, and don't need this real-time behavior, you can compile your model at a faster rate than what you are running your system at.  In this case, the amount of time that passes in real life will not equal the simulation time.

From your description, it sounds like this is what you're actually doing.  I find it hard to believe that you were able to get your VeriStand system to run at 100 kHz, so I assume that the model was compiled at 100 kHz, but your system is set to some other (slower) rate.  If this is the case, it may be sufficient to just change your system rate to something slower (again, this is set on the "Controller" page of the System Explorer in NI VeriStand).  This will give your model more time to finish execution, and will prevent it from finishing late.

Another option would be to change the Execution mode (also on the Controller page) from Parallel to Inline.  This will cause the primary control loop to wait for the models to finish execution before moving on, so you will not see the Model Count increase.  However, this introduces the possibility of causing your entire primary control loop to finish late, so you my see the "HP Count" system channel start to increase.  Obviously this affects the determinism of your system, and could cause problems if you are actually doing any hardare I/O.  However, if everything is purely in software (ex. model-in-the-loop simulation), this may not be a problem for you.  Again, you can also slow down the system rate to give the models more time to complete, and prevent the "HP Count" from increasing.

Hopefully I understood your situation correctly, but if not, please let us know what exactly are you trying to accomplish with your system and model?  Why do you need such fast model rates, and what are these models connected to in your system?

[Debz]

Thanks Devin_K.

That's not exactly what I'm doing.

I will be doing a hardware-in-the-loop simulation so my model I/O will need to be map to hardware I/O. So I need to run the model in "real time".(model step size = Veristand rate)

When I deployed the 10kHz and 100KHz model, the Veristand rate was respectively 10KHz and 100KHz.

But for the moment I'm just trying to figure out the maximum rate in "real time" I can achieve. With the PXI-8106 dual-core controller it is around 10KHz.

If I understood well, by going with a PXI 8133 quad-core the maximum rate in real time (model step size = Veristand rate) will be around 10KHz too?

[Devin_K · Accepted solution]

Hi Debz,

It depends on the model and the hardware setup, but no, I wouldn't expect to see more than 15 kHz on an 8133.

However, there are a couple of other options which might be possible to achieve faster rates.

1.  We have been working on on a custom device internally which runs the models outside of the normal VeriStand framework at a much faster rate.  The VeriStand engine still runs at slower rate (ex. 1 kHz), but a separate loop is taking a DAQ input, executing a model, and writing a DAQ output.  This model runs at a much faster rate, and communicates the current values back to VeriStand at the VeriStand engine rate.  With this technique, we have been able to run reasonably complex models on an 8133 at around 50 kHz.  Simpler models have been run close to 140 kHz.

Depending on your setup, this might be a possibility for you.  If you're able to provide us with your model (preferably the .mdl file, so we can make sure it's compiled optimally), we could benchmark it for you and give an estimate for the maximum rate we can run it at.

2.  Based on your description of the model, it sounds very simple.  Simply a voltage/current regulator.  If this is the case, perhaps this logic could instead be implemented on a FPGA board instead of a model.  The FPGA could read an input, perform the regulation, and write an output without requiring any resources from your RT processor.  Provided the math wasn't overly complex, you could run this VERY fast.  However, I still don't think you would be able to achieve 10 MHz.  The limiting factor would likely be the analog sampling rates on our FPGA boards.  The PXI-785XR boards can sample AI at 750 kHz, and output AO at 1 MHz.  If we're talking about analog signals, it would be tough to find something much faster than that.  If it's just digital TTL signals though, they can go much faster on that board (ie. 40 MHz).

I'm still curious as to what your application is and why you need all of this running at these rates.  If we had a better understanding of your application and what you hope to accomplish, perhaps we could provide some better guidance.  If you'd like, you can send me a private message with your contact info, and I can get you in touch with a resource in your area who specializes in these application areas.

Regards,

Devin

[Debz]

Thanks very much Devin_K.

1. For the moment I only have a simplified version of the model. But when when I will be provided with the real one I would like a benchmark. I never did custom device but I'm interested in your way of running the model outside the Veristand framework. Can you provide me the custom device or give me more details ?

2. In fact I have been asked to run the model on the controller but It could be a good idea to try to implement the model on the FPGA.

I will need both analog and digital I/O of the FPGA board.

A similar HIL simulation have been done here at a very fast rate (10MHz). But it is not implemented on National Instrument hardware and software.

That's why I wondered if it was possible to achieve such a rate with Veristand.

When i'll have more information i'll send you a private message. Thanks

[Devin_K]

I believe the custom device uses parts of the Simulation Interface Toolkit to call into the model DLL, but I haven't actually seen the code myself and the person who worked on it isn't in the office today.  I look forward to hearing back from you