PCL Target Rate

[Tidus]

Hello

I have cRIO 9014 with NI cRIO-9103 chassis.

Modules:
NI 9263 AO,

NI 9481 RLY,

NI 9422 DI

I used local variables on FPGA code to run PCL faster.. (attached FPGA code and other screenshots)

It works fine at target rate up to 500Hz..

But it doesnt work higher target rates..

Giving an error.. and this make cRIO stuck.. it doesnt work next Run even if I change target rate back to 100Hz.. Only way to get rid of this is

- Reset cRIO

- Remove bitfile from RT host via web browser before communication lost again.

I am kinda new with Labview and Veristand.. What do I do wrong? Anyone can help please?

Thanks

Veristand Error:

• Loading System Definition file: C:\Users\Public\Documents\National Instruments\NI VeriStand 2010\Projects\XXXX\XXXX.nivssdf
• Initializing TCP subsystem...
• Starting TCP Loops...
• Connection established with target Controller.
• Preparing to synchronize with targets...
• Querying the active System Definition file from the targets...
• Unloading System Definition file...
• Connection with target Controller has been lost.
• Loading System Definition file: C:\Users\Public\Documents\National Instruments\NI VeriStand 2010\Projects\XXXX\XXXX.nivssdf
• Preparing to deploy the System Definition to the targets...
• Compiling the System Definition file...
• Initializing TCP subsystem...
• Starting TCP Loops...
• Connection established with target Controller.
• Sending reset command to all targets...
• Preparing to deploy files to the targets...
• Starting download for target Controller...
• Opening FTP session to IP 10.0.0.190...
• Processing Action on Deploy VIs...
• Gathering target dependency files...
• Downloading XXXX.nivssdf [129 kB] (file 1 of 3)
• Downloading XXXX_Controller.nivsdat [72 kB] (file 2 of 3)
• Downloading cRIO-9103 Deneme 4.lvbitx [1750 kB] (file 3 of 3)
• Closing FTP session...
• Files successfully deployed to the targets.
• Starting deployment group 1...
• Connection with target Controller has been lost.
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:
Error 56 occurred at Project Window.lvlib:Project Window.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

LabVIEW:  The network operation exceeded the user-specified or system time limit.
=========================
NI VeriStand:  TCP Open Connection in Server TCP Interface.lvlib:TCP Connection Manager.vi:1

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
• Unloading System Definition file...

[ThSa]

I don't think that you necessarily do anything wrong, I rather think that you have hit the maximum performance of the cRIO. The timeout error occurs since the PCL (which is actually a timed loop) tries to keep up with the user configured rate which let's the data processing loop (also a TL but with a lower priority) starve. The things that you can do and try to improve the performance is to install only the necessary drivers/software on the cRIO system (delete the scan engine, shared variable engine and all other stuff that is actually not needed). If you run a simulation model, check if you have to run it every iteration or is it possible to increase the decimation?

You might also want to look into things to reduce the memory footprint overall - for example lower the number of streamed channels on the controller page itself and also increase the decimation rate of the data processing loop. Although, I don't think that latter will give you really a huge boost.

Other than that, if you don't hit the expected performance, you might want to start looking to get a more powerful controller.

There is actually an easier solution beside deleting files from the cRIO to get access again after the cRIO rebooted. In System Explorer you gotta select the last node in the tree called 'System Initialization'. On the tab control switch to the 2nd tab called 'RT Target Reboot Action'. I am sure that 'Run System Definition' is selected in your case. If you flip the checkbox to be 'Wait for Deployment' the NIVS engine won't start automatically.

Tom

[Tidus]

Hello

Since it is not possible to log data at 4kHz with NI Veristand, I decided to use one cRIO 9074 to log data at 4kHz with Labview FPGA project, another one for NI Veristand. I also want to communicate 2 cRIO to reach all modules and start/stop logging data via NI Veristand. This is possible via Network-Published Shared Variables? If not what would you suggest me?

Thanks

[MegaHertz]

Hi Tidus,

One quick question for you. Have you considered using the Embedded Data Logger custom device? As explained on the linked page, adding this into your System Definition will allow you to implement the data logging directly in your system. Have a look at that to see if it might work for your needs.

Good Luck!

Andy H

[Tidus]

Hello

First Thanks for your reply..

I have used Embedded Data Logger Custom Device. But it is working in PCL (Inline HW or Model Custom Device). This means I cannot reach to 4 KHz to log data..

I have managed to use network-published shared variables to communicate 2 cRIO with veristand. So it seems there is no problem for now... If I encounter another problem I will ask here 😃

Thanks.