Relationship between "HP-Loop Duration" System Channel, number of DAQ channels used with a MUX board.

[Vincent_R.]

Hi,

I'd like to get a better understanding of how the DAQ part of the NIVS engine works on the RT target. In fact, my customer uses couple of PXI-6259 boards and I'd like to know how the code is implemented under the hood.
Why?
With a new System Definition with only this DAQ board (controller-rate set at 1 kHz), 8 channels used, the "HP-Loop Duration" equals about 70 us on my PXIe-8108 controller. Same System-Definition but with 16 channels, it jumps to 159 us.

My first question is: we don't seem to use the maximum AI-Convert rate of the board (1 MS/s aggregate). Am-I right? If YES, why? I understand that because of increasing number of channels, it's going to be longer to scale and refresh the NI-VS tables but my guess is that it's mainly due to a longer acquisition time. I did a quick test in LabVIEW-RT and it seems that the default AI-Convert Rate is not the maximum (1 MHz) but something like 90kHz.

My second question is: the code is something like a while loop (or timed-loop), hardware-timed. If YES, what type of event does awake the loop?

Is-it "Sample-Clock" or "Sample Complete Event" or something else... I think it's "Sample-Clock" because the "HP-Loop Duration" varies with the number of channels used (and I'm using a board with only one ADC). Am-I right? If YES, is-there any reason why? Maybe it's because of CPU load or something else.
As the variation is quite important, I'd like to get an explanation. Maybe my test is not valid.

Best regards

Vincent

[Ben_J1]

Vincent,

   These are interesting questions. As for if we use the maximum AI-Convert rate we do not. We use hardware-timed single-point to gather things like

Analog Input. Here's a KB on it:

Data Acquisition Hardware Compatibility with NI VeriStand

http://digital.ni.com/public.nsf/allkb/6BC224FE529A9C65862576430077E004

What are you referring to in your second question about an event awakening the loop? The loop iterates sequencially through a number of steps, one of which is reading from the daq devices. 

Regards,

[Vincent_R.]

Hi,

NIVS engine is based on LV and timed-loop.

When you used timed-loop, you can make them hardware-timed and you can choose which event to use to awake your loop, that's what I'm referring to.

Regards

Vincent

[ThSa]

Vincent,

Let's see if I can answer ur questions.
The reason why we didn't expose a setting to determine the Conversion time of any of the boards is due to the simple fact that it wouldn't matter. The slowest component is the code that is executed within the pcl loop which determines the max speed. Even if we would have exposed that property, it wouldnt have changed the performance. In other words, each board us used with its default conversion rate based on the number of configured channels.

In regards to ur 2nd question. We do use sample clock. Hereby we simply determined which mechanism works the best. based on our results we decided to export the sample clock as clock source for the tl.

If u think that it is valuable in either case to have users configure either of the above discussed items, pls feel free to file a car to me.