Synchronize several timed loops with the Veristand engine

[aRCo]

Hi all,

i'm working on a custom device made of a RT driver containing several timed loops. For each custom device i set dt with a value of 1 ms.

What i would like to do now is to synchronize the loops with the Veristand engine (which works at the same rate of 1 ms).

Is there a way to do this? For example, could it be possible (double clicking on each time loop and opening the "Configure timed loop" window) specify a different source name which points to the Veristand engine timing source?

Marco

[StephenB]

in your configuration code somewhere call this VI:

http://zone.ni.com/reference/en-XX/help/372846D-01/veristandmerge/vs_set_loop_type_vi/

Make sure "loop type" is set to timed loop and "use device clock" set to true.

Then in your RT code, make sure you have the string control "Device Clock" on your front panel. Wire that into your timed loop(s) and they will be sourced from the same clock as the NIVS timed loops.

[StephenB]

Actually I should be more clear. That device clock string is not the same exact string the primary control loop uses, rather... it is a software source that the primary control loop will tic when it is done writing to the async device.

So the PCL will wake up, do work.... write to the async device... then tic the async device timing source. Therefore there will be a small delay between when the PCL wakes up and the async device wakes up.

[Jarrod_S.]

Also when using this timing source set the dt to 1, because the period in this case is measured in number of periods of the Primary Control Loop. So a dt of 1 implies you want the loop to execute every time the PCL executes. A dt of 2 would imply every other time, for instance.

[StephenB]

Yes good point... I see a lot of people leave this at the default of 100 and end up with a decimation of 100 unknowingly.

Another way to do it is to use the "set decimation.vi" on the configuration and the "get decimation.vi" in the engine to get the timed loop dt value.

[kabooom]

If i create a Timing and synchronisation custom device.In this custom devcie, i created a Timing source and i generate this signal on RTSI0.

- I Parameter the chassis to use this custom device as master hardware synchronisation.

- I Parameter the Timing source of the controller (set the primary control loop timing source to use my custom device).

So if i'm correct, that means the PCL will use the Timing source created in the custom device. When you create parallel timing loop using the device clock, will these parrallel loop also use the same Timing source ? Or Veristand engine create another timing source from the original one (you wrote we will have a delay between the PCL and the asynchronous loop) ?

The other question is what the aim of the RTSI0? In Veristand i found that you have to overwritte the RTSI0 when you create a timing and synchronisation custom device, but why is it used for ? Does the engine create a timing source from RTSI0 signal ?