09-19-2014 04:12 PM
I am having an issue with timing/synchronization using the myRIO. To describe the problem, I'll first describe my application. I am essentially trying to continuously measure how long an object phosphoresces (i.e. glows in the dark) after being illuminated by an LED. The is performed as follows. The LED is driven using a square wave input that lasts 500 us. While the LED is on, it is optically exciting the phosphorescent object. Immediately after the LED is turned off, a photodiode is used to measure and record (via myRIO) the light intensity emitted by the phosphorescent object, which follows a very predictable exponential decay lasting around 20 us. To reduce the effect of noise, this process of turning the LED on, then off, and then recording the light intensity emitted by the phosphorescent object is repeated 25 times, and the 25 data sets corresponding to the decay of light emission from the phosphorescent object are averaged together.
Most the important steps above are deployed on the FPGA using the code shown above. My goal is to control the timing of the sequence by adding the loop timer @ 2us (even though I am forcing the first two frames of the sequence to stall for 10,000 us and 500 us, respectively). DIO0 on connector C is turned on and then off to control the LED. In theory, 2 us after the LED is turned off, data from the photodiode is then read every 2 us for a selected number of samples (default = 100). This is achieved by sticking the values into a FIFO buffer within a for loop that I am again trying to force to run every 2us (500kHz).
This process is repeated using labVIEW code deployed on the myRIO shown below, which is how averaging is achieved.
So this is where the problem comes in. When I start the program running on the myRIO (which calls the VI deployed on the FPGA), everything seems to work fine. An example of the data collected after monitoring the intensity from the my phosphorescent object 25 times is shown below. Although not entirely clear, there are 25 data sets (exponential curves) that overlap quite well, as they should since I am just repeating the same measurement 25 times. For this to work properly, again, the synchronization between turning the excitation LED off and recording the photodiode data thereafter must function properly.
However, after the code runs a hundred iterations or so (i.e. 100 or so averaged curves are collected), things start to go wrong. For some reason, the synchronization between turning the LED of, then off, and then collecting the phosphoresce data goes awry. Specifically, I start to get curves that look like the image below. As you can see, I still get the exponential signal that I expect from the phosphorescent object, however, the data is no longer synchronized in time (i.e. the peaks of the exponentials no longer line up as they did before).
Strangely, if the simply let the code continue to run, the curves will eventually sync back up perfectly, and the code with run as intended for another 100 or so iterations before the same issue occurs. This pattern repeats indefinitely.
If anyone would be able to help me troubleshoot this problem, I would really greatly appreciate it.
P.S. Code in question is attached.
09-19-2014 04:14 PM - edited 09-19-2014 04:14 PM
Just is case code didn't attach to previous message....
09-22-2014 03:23 PM
Hi seanmw,
It seems that your host VI works properly for one iteration of the For Loop that governs the main code. You are opening and closing the reference to the FPGA each iteration for 100 iterations. You could try moving the open and close FPGA reference VIs outside the For Loop and just call it once for the host VI. In order to still be able to switch between the LEDs, you can put all of the code into one FPGA VI and use a Read/Write control to turn the correct LED on/off.
09-24-2014 01:39 PM
Hi BobRodge,
Thank you so much for your help with this issue. I moved 'Run' and 'FIFOstop' outside the for loop in the host VI, and ran the host VI for a few hundred iterations. It would seem that the problem is solved! I really appreciate the suggestion! I see what you were referring to about opening and closing the FPGA reference 100 times. Any idea why this may have caused the behavior I was experiencing? I can't seem to get my head around it. Regardless, thank you again for solving the issue,