issue instantiating Xilinx IP with myrio

[jaimefmNI]

I am having trouble instantiating any items from the Xilinx IP palette into my projects. i believe i have all the required software installed, but there is still an error that says, "No user IP repositories specified", even though i do see IP functions in the directories it says its looking in. So it does not allow me to configure any Xilinx IP.  

Any other settings i am missing? I am able to compile and run projects that do not use Xilinx IP.

I have the myrio-1900, running in windows 8.1.

below is the output i get after pressing the "Configure Xilinx IP" button for the floating point IP block. (Found in Xilinx IP -> Math Functions).

C:\NIFPGA\iptemp\xipinBD40ED244EE942F7BF92AF0DE2FF7A66>set XILINX_EDK=C:\NIFPGA\programs\Vivado2013_4\ids_lite\ISE

C:\NIFPGA\iptemp\xipinBD40ED244EE942F7BF92AF0DE2FF7A66>cmd /c C:\NIFPGA\programs\Vivado2013_4\bin\vivado -mode batch -source "C:\NIFPGA\iptemp\xipinBD40ED244EE942F7BF92AF0DE2FF7A66\init.tcl"

****** Vivado v2013.4_(AR59519_AR59812_AR59814_AR60501) (64-bit)
  **** SW Build 353583 on Mon Dec  9 17:49:19 MST 2013
  **** IP Build 208076 on Mon Dec  2 12:38:17 MST 2013
    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: Implementation
WARNING: [Common 17-301] Failed to get a license: Implementation
WARNING: [Vivado 15-19] WARNING: No 'Implementation' license found. This message may be safely ignored if a Vivado WebPACK or device-locked license, common for board kits, will be used during implementation.

Attempting to get a license: Synthesis
WARNING: [Common 17-301] Failed to get a license: Synthesis
Loading parts and site information from C:/NIFPGA/programs/Vivado2013_4/data/parts/arch.xml
Parsing RTL primitives file [C:/NIFPGA/programs/Vivado2013_4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [C:/NIFPGA/programs/Vivado2013_4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
source {C:\NIFPGA\iptemp\xipinEA40085D63A44A87A9EE514E55C4BD3C\init.tcl}
# set tempdir {C:\NIFPGA\iptemp\xipinEA40085D63A44A87A9EE514E55C4BD3C}
# set prjdir $tempdir\\temp
# set ipname Floating_dash_point_F16386491B674413A51B6154E16AFC29
# set ipdir  $prjdir\.srcs\\sources_1\\ip\\$ipname
# set simprjdir  $tempdir
# set simdir $tempdir\\sim
# set simproj $simprjdir\\$ipname\.prj
# set simvhd $simdir\\$ipname\.vhd
# set simvhdports $simdir\\$ipname\_ports\.vhd
# create_project $prjdir -part xc7z010clg400-1 -force
# create_ip -vlnv xilinx.com:ip:floating_point:7.0 -module_name Floating_dash_point_F16386491B674413A51B6154E16AFC29
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/NIFPGA/programs/Vivado2013_4/data/ip'.
# close_project                   
# open_project $prjdir         
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/NIFPGA/programs/Vivado2013_4/data/ip'.
# set user_ip [lindex [get_ips] 0]
# upgrade_ip $user_ip
WARNING: [Coretcl 2-1044] upgrade_ip is not supported by 'Floating_dash_point_F16386491B674413A51B6154E16AFC29'
# set_property IP_OUTPUT_DIR $tempdir [lindex [get_ips] 0]
# set ipvlnv [get_property ipdef [get_ips $user_ip]]
# set ipfile [get_property IP_FILE [lindex [get_ips] 0]]
# set lic [get_property REQUIRES_LICENSE [get_ipdefs $ipvlnv]]
# if {$lic} {
# set fp [open $ipdir\\needlicense.txt w]
# close $fp
# }

    while executing
"start_ip_gui -ip $user_ip"
    invoked from within
"set ip_name [start_ip_gui -ip $user_ip]"
    (file "C:\NIFPGA\iptemp\xipinEA40085D63A44A87A9EE514E55C4BD3C\init.tcl" line 24)
INFO: [Common 17-206] Exiting Vivado at Fri Dec 26 10:10:21 2014...

[Myr.i.am. · Accepted solution]

Hi jaimefmNI,

I'm having some trouble replicating this behavior on a Windows 7 PC.  Would you mind posting the exact steps you're taking before the error occurs?  When you drop down the Floating-Point 5.0 function and select "Configure Xilinx IP," are you taken to the Floating-Point Dialog Box, or do you receive the error immediately?

I should also mention that the LabVIEW 2014 FPGA Module is not compatible with Windows 8.1.  Please see the linked Readme for more information:

LabVIEW 2014 FPGA Module Readme: http://www.ni.com/pdf/manuals/374737a.html

Thank you,

Myriam

[jaimefmNI]

Thank you for pointing out that Labview 2014 FPGA is not compaitble with Windows 8.1. That is likely the source of the problem. I did install Labview FPGA on a machine with Windows 7 and i did confirm that i could configure and place Xilinx IP on myrio.

With my current setup running in Windows 8.1 when I drop down the Floating-Point function and select "Configure Xilinx IP", I am NOT taken to a Floating-Point Dialog Box. the progress bar shows some progress while the log that i copied to my previous post is generated. then the progress bar stops, goes back to 0% and i am only given the option to cancel the properties page.

I guess i was thrown off because i have been able to compile other projects that did not use Xilinx IP..

Once again thanks for pointing out the problem with my setup...

[Myr.i.am.]

No problem, good luck with the rest of your application!

Myriam

[Salinger86]

I've solved the problem running Labview in compatibility mode (Windows 7) in windows 8.1. This is easier than using a Virtual Machine!