myRIO blank custom FPGA VI takes up 63.5% of FPGA capacity?

[Tym_Zhu]

I am currently developing custom FPGA project with myRIO and always exceed "Slice LUTs" limitation.

Further investigation reveals that even a blank VI (not the defult one) could use 63.5% of Total Slices.

Is it because LabVIEW methods need these huge space or it's just because I didn't get the options right?

[Tym_Zhu]

Just found similar post..

http://forums.ni.com/t5/Academic-Hardware-Products-ELVIS/MyRIO-simple-code-compilation-FPGA/td-p/283...

[Kristoff2]

I just came here to link to that thread 😄

Let us know if you have any questions about that.

Thanks!

-Sam K

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