myRIO block FPGA compilation

[BiedaK]

Hello,

I have a problem that my FPGA do not remeber that it has been compled before.
I have made a program on myRIO FPGA and I do not want to change it.  Only to run it and check how it is cooperating with RT VI, that I change.
I need hardware compilation for my FPGA( not simulation) to oserve how signal transmits.

How to block FPGA compilation ( when the VI is not changed inside) to not be compiled every time that I work with the project?

[ValkoA]

Dear Bieadak,

if I undestood corectly, you are working on a Real-Time code that opens the FPGA VI with the FPGA API. The simplest thing to do in this case would be to set up the Open FPGA Reference.vi to use the bitfile (or the build specification) instead of the VI.

Here and here you will find some documentatin on that. 

Kind regards: