aaaand I just discovered Snippets ಠ__ಠ... What features did you wish you had come across earlier?

[GregFreeman]

Cloning (ctrl+click+drag) vs copy-paste...especially with property nodes and local variables!

[thoult]

Am I right in thinking that doing this with timed loops is a no-no?

[crossrulz]

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@thoult wrote:

Am I right in thinking that doing this with timed loops is a no-no?

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What are you referencing?  Doing what with timed loops?  Did I miss something?

[thoult]

I vaguely remember having issues with multiple timed loops in a VI (code not executing in some loops IIRC), and the only way I could guarantee it not happening was to create a new instance of a timed loop from the palette rather than click-ctrl-drag to copy.

[GregFreeman]

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@thoult wrote:

I vaguely remember having issues with multiple timed loops in a VI (code not executing in some loops IIRC), and the only way I could guarantee it not happening was to create a new instance of a timed loop from the palette rather than click-ctrl-drag to copy.

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Hm, I'm not sure. I don't use timed loops that much, unless I'm on FPGA. On RT I don't find them very helpful because I'm usually acquiring and buffering data (whether using DMA FIFOs or DAQmx reads) and I can deal with slight amounts of jitter because the acquisition itself is still deterministic. In fact, not to derail this thread, but I'm curious on what others are using timed loops for. Are a lot of people doing software timed acquisition/generation where jitter needs to be kept to a minimum?

I'd be interested if you could reproduce this issue though, just so I know for my own knowledge if I run across an issue when cloning timed loops.

[thoult]

I use timed loops on the host side of an FPGA system to buffer incoming samples.

The FPGA target fills a FIFO with six channels of analogue data every loop, and the host empties this FIFO every 10 ms inside a timed loop. The data is passed into a functional global that builds an array of the data until the array length is greater than the desired packet length. The packet length's subset of data is offloaded and the remainder is retained to build the next packet.

This way, I can sample data at 100 kHz on the FPGA, dump it reliably into the FIFO, then retrieve it at (roughly) every 10 ms. It doesn't matter if my 10 ms loop is slightly early or late, as the FGV will only offload a packet of 60000 elements (i.e. six channels interlaced, sampled at 100 kHz, every 0.1 s on my host). Any data not included in the first packet is retained for the next packet, and because I set the packet length I ensure the data order is maintained.

I'll see what I can reproduce with regards the timed loop copying, but I distinctly remember having issues in the past with timed loops 'corrupting', for want of a better word.

[GregFreeman]

Running code on a remote system (PXI Chassis, cRIO, etc) in the development environment, you can right click and disconnect from the target in the project. The code on the target will continue running. If you right click the target and reconnect, it will relaunch the front panels of the running VIs so you can continue debugging. Debuggable executables before delivery no more!

Great for when you want to leave something running overnight or for the weekend then see what the panel is showing when you get back to the office on Monday, but don't want to leave your computer at the office.

[PaulG.]

I still remember how thrilled I was years ago to find the diagram disable structure. Before then I was putting disabled code inside of a False case structure.