Gate inputs on 6602

[jonny e]

Hey everyone,

Have a peculiar problem I just can't seem to figure out.

I have a 6602, using Labview 7.1 (i know, i know, i'm a technological neanderthal).

Anyway, my problem is this:

I have some homemade electronics that outputs a 5V pulse which should trigger pulse train generation on the falling edge.

For counters 0 and 1, this works just fine.

However, for any other counters 2-7, I can't generate hardware triggered pulses.  I've discovered the reason is that anytime I wire my trigger pulses to any of counter gates 2-7--or any other PFI lines other than those dedicated for counters 0 and 1--the trigger pulse I measure is of order 2V amplitude...much smaller than the 5V I would expect. 

Thus, the amplitude of the trigger pulse is not large enough to actually trigger these counters. 

This problem happens not only with my homemade electronics, but with pulses output by PCI-6071E.  If I generate a pulse train on one of its counters and try to use these pulses as the inputs to any of gates 2-7 on the 6602, I see a lower amplitude signal again as if there is some voltage divider action.  Again, using the 6071E pulses input to gates for counters 0 and 1 on the 6602 works just fine.

Any ideas what could possibly be happening here?

I know that counters 0 and 1 are dedicated counters, while the others share function with DIO lines and encoders.  I wonder if something is configued incorrectly? 

Any suggestions would be very appreciated, as I'm at a total loss for why this is happening.

Thanks!

[jonny e]

An update on my previous post.

I discovered when I power cycle my computer or just exit from labview, then reload it, the problem goes away.  I.e. the 6602 card behaves as expected, no issues whatsoever.

Furthermore, I have discovered that the problem only comes back when I run my other file "neurochip-legacy.vi" which is attached to this post as a .zip file.

When I run this vi, I see my trigger signal immediately go from 5V to 2V.

Thus, I think something is getting configured funny in that file which is affecting how my PFI/gates work.

For anyone who is kind/brave enough to look through it, there's a lot of irrelevant stuff.  The parts that are probably relevant and affecting me are in the first frame (frame 0 of the outter most frame, where I configure the 6602 for 32 bits of DIO. 

Later, in outter frame 3, inner frame 3, false case, the 6602 is used again to produce output pulses on counters 0 and 1.

These are the only times the 6602 is used in this vi, and I suspect something is getting screwed up in the configuration with the DIO lines.

Any thoughts/comments/suggestions would be much appreciated.

[AnalogKid2DigitalMan]

jonny e:

Your post did not include an attachment

[jonny e]

whoops, i must've forgotten the first time. it shoudl be attached now

[jonny e]

One more comment/update: 

I know my problem occurs when the DIO Port Config is called in neurochip-legacy.vi

I wish I could set just the 8 dedicated DIO lines for output, but the port width must be specified as 32.  Trying to enter a port width of 8 results in an error.  Apparently this device doesn't have the capability to be configured for just 8 lines of DIO and leave the shared counter lines untouched?

Still, I don't understand why I can't subsequently configure these for use with counters..

[Kevin_Price]

I don't have LV at my network PC, but I think the posts have now given me enough clues to suggest what to do.

1. The call to DIO Port Config *can* set the dedicated 8 DIO lines as outputs while setting the other 24 as inputs.  One of the input terminals takes a bit-mapped input to specify which of the 32 bits should be inputs and outputs.  Most of the examples wire it either with a 0 (meaning all bits are 0 for all inputs) or with a -1.  The bit-wise representation of the value -1 turns out to be 32 binary 1's, meaning all bits are 1 for output.

The specific way to set the lowest 8 dedicated DIO bits as outputs with the other 24 as inputs is to wire in the decimal value 255 which fills only bits 0-7 with binary 1's.  If I remember right, the input in question has a name like "line map" or "direction map" maybe?

2. The vi DIO Port Config uses the traditional NI-DAQ driver.   If your newer app uses DAQmx driver calls, that's another issue to deal with.  A given board can't be simultaneously called with both drivers, and a special call to perform a board reset needs to be called if you switch from one to the other.  Such a board reset probably guarantees that DIO outputs set by the old vi will get reset to defaults.

So you either need to make sure your newer app uses traditional NI-DAQ functions, or make both of them use DAQmx.  DAQmx is definitely the better choice for future compatibility, but you may need to weigh that out against the learning curve in the short term.

-Kevin P.

[Jarrod_B.]

Hello Jonny,

I think you've done some great debugging to isolate the problem.  You're absolutely correct in your observations.  The only way that a digital line could pull your external 5V signal down is if it was trying to drive that line low, meaning it's configured as an output.  With the DIO Port Config VI, there is an input called line direction map.  You can use this to specify which lines to use for output, and which ones to use for input.  I saw in your code that you had this input set to -1, which configures all the lines for output.  This would explain the behavior you're seeing.  If you change this to only set Port 0 for output (I believe the map would be 255), then your application should work. 

For more information see the following Knowledge Bases:
Some NI 660x Counters Do Not Function Correctly When Performing Digital I/O
How Do I Configure the PFI Lines on the PCI-6602 for Digital I/O?

Also, there is an Example Program that demonstrates the concepts described in these KBs:
Pulse Train Generation and Digital Output on a 660x

Let us know if this works once you try it.

Best regards,

Message Edited by Jarrod B. on 03-16-2007 10:41 AM

[jonny e]

Howdy everyone, Thanks for all the feedback. 
Indeed the conflict with DIO port config was the problem.
My device was trying to drive the line high and the DIO port config was trying to tell it to output low--that's a backyard brawl!

The line direction map works as promised and now all is working! The reason I originally thought I could not use the line direction map was that the documentation for DIO port config says: "The AO-2DC, 6704, 673X, 671X, 653X, DSA, and E Series devices are the only devices on which you can configure lines within a port for different directions."
The 660x devices should also be included in this list, no?

 Thanks again everyone for all your help!