Getting 2nd TIO of the PCI6602 to perform buffered event counting via register-level programming

[al_waes]

I got the first PCI6602 TIO to perform buffer event counting using interrupt. However, I could not get the second TIO working. I think I have initialized the proper registers in order to work with the second TIO, i.e.

1. Addressing all registers of the second TIO at 0x800 offset.

2. Binding the clock to counter 4-7 (set 0x00200000 to the Clock Configuration register). I am using the internal Timebase_3 clock which is 80MHz.

3. Tried setting 0x8000 to the Global Interrupt Control register at both its offset location (with 0 offset) and with 0x800 offset (2nd TIO offset location).

Am I missing something here? I got no interrupts from the PCI bus and I got 0xff
ff when I tried to read the Status register.

[Tim_Ousley]

Al,
Try writing a 0xA0000000 to the Global Interrupt Control register for TIO(0). This enables an interrupt from TIO(1) to cascade through TIO(0).

[al_waes]

Tim,

Thank you for your tip. I finally got the interrupt working on the second chip TIO(1). Besides writing 0xA0000000 on the Global Interrupt Control register for TIO(0), I also have to write 0x80000000 on the same register for TIO(1).

I hope all this will be explained in the new 66x RLP manual. I understand the copy I received is still preliminary. It doesn't contain any information about setting up interrupts.

[Rob Russell]

Al,

I have been experimenting with the 6602, but I have not been able to see any of the interrupts generated by the counters. I have tried both TC mode and an external signal on a single GATE (G0). The Gi_Status_Register indicates that the interrupts are occuring (appropriately for each mode), but I can't see them on the bus (my interrupt handler is never invoked; cat /proc/interrupts shows 0 interrupts).

Could you pass along any tips on how you did it?

Thanks!

-Rob