How would I output the same square wave signal I aquire?

[Nave]

Hi:

     I'm using a NI PXI-6602 Timing I/O card.

 I have a 7.2K Hz TTL square wave that comes from an encoder on my generator. I want to put this square wave on a backplane line (ex..PXI_Trig0) so that I can use it as a trigger for my digitial I/O card. How do I get out the same signal I put in? I was thinking I would have to use "retriggerable single pulse generation"

I also have a 21.6K Hz TTL square wave that comes from an encoder on my generator. I also want to put this square wave on a backplane line (ex..PXI_Trig1) so that i can use it as a clock for my digital I/O card. However, I need to be able to pause this clock signal if my enable signal goes low for any reason. I was planning to aquire my digital enable signal on PFI0 and route it to a backplane line (ex..PXI_Trig2). How do I get out the same signal I put in and pause it if need be?

[Kevin_Price]

It's likely that these routings can be accomplished withtout any special programming.  For example, suppose your 6602 is Dev2 and your DIO card is Dev1.  Then when you configure your digital task on Dev1, you can probably directly configure it to use the encoder signal as a trigger, with syntax similar to "Dev2/PFIx".  Same for the other encoder as an acq clock.

However, some routings won't be possible and I don't have the resources handy to double check these particular ones.  If you have to handle this manually, your idea of using "retriggerable single pulse" generation is likely the best way to go.  Just realize that you probably won't be producing true 50% duty cycle square waves.  You probably won't want to anyway.  For trigger and acq clock purposes, you probably want to define minimal low and high times to minimize delay.

Normally you would use "pause triggering" to pause an acq clock but I think it might not be possible to configure both an edge-sensitive start trigger and a level-sensitive pause trigger on the same DIO task. 

Hmm, sorry, I shoulda read the whole thing before answering in parts.  Is it a single DIO task that needs both start triggering *and* pause triggering?   If this can't be accomplished directly in hardware, you may need to approach this as a problem to be solved with post-processing.  Let me ask a couple more questions:

1. Why exactly are you triggering off the 7.2 kHz encoder?  Are you using that encoder signal *only* as a trigger?  Do you need to trigger off the very first edge it generates?  Or are you triggering from it for another reason (sync, confirm that it *is* generating, etc.)

2. Why do you need to pause acquisition when the enable goes off?  One workaround would involve capturing the enable signal to timestamp the on and off times, then filtering out acq data that occurs when the enable is off.

-Kevin P.

[Nave]

Hi:

     I guess you can simplify it as a single DIO task that needs both start triggering and pause triggering. However, as you hinted I don't think this can be done with the hardware. I was thinking I could have a single DIO task that uses a start trigger and I could pause / resume the clock signal I use for the task. I haven't tested it but I believe I do know how to set up a task that uses both an external trigger and a clock source.

1. The 7.2KHz square wave is an marker pulse from the generator, I use it for synchronization. It is only being used as a trigger and I do not need to trigger off the very first edge. I simply need to start outputing when a marker pulse occurs.

2. The enable signal is an emergency stop feature. If anything goes wrong this line can be dropped low and multiple devices will be tripped, de-energized, and stopped. With my hardware, if this line goes low, I should pause the task.

[Nave]

Hi:

     I ran into a 1997 DIO user manual in our office for a NI PXI-6533. It talks about triggered pattern-Generation Timing. I've attached a scanned page. It has a start trigger line, a stop trigger line, and a request pulse line. I think this may be what I want to. Use my 21.6K Hz signal as my request pulse. Use  my 7.2KHz signal as my start tirgger, and use my enable signal as my stop trigger. Does anyone know of a good example on how I would set this up? Also, will the task restart on the next start trigger after my stop trigger has occured?

I think it would be nice to use the retriggerable single pulse generation to buffer both my encoder pulses. However, is it easier to get the signal on a backplane line (PXI_Trig0, PXI_Trig1) then I originally thought? I saw the VI "DAQmx Connect Terminals.vi". Can I connect the 21.6KHz signal on the source for counter0 and then simply use "DAQmx connect terminals.vi" to route it to backplane signal PXI_Trig0? It would appear that I'm not using the counter for anything, so would I even need a task?

[Kevin_Price]

I'm not at all familiar with the 6533 board -- hopefully someone else can help there.

Usually you *can* route signals from one board's PFI pins, up to RTSI / PXI Trigger lines, then back down to another board's task without having to define a specific DAQ task to help do it.  DAQmx can do quite a lot of the management under the hood.  As I mentioned before, it's often literally as simple as wiring in a signal like "Dev2/PFIx" to the DAQmx Timing vi that you use to define the sample clock for your Dev1 digital task.  (Or similar with the DAQmx Trigger vi).

Meanwhile, I can describe a way to accomplish edge triggering with a pause-able sample clock.  You'll have to use a couple of your 6602's counters.

1. Configure your digital task to use the 7.2 kHz signal as a digital start trigger.  This can probably be done the easy way as outlined above.

2. Futher configure your digital task to use the output of Counter 0 as its sample clock.

3. Configure Counter 0 for retriggerable single pulse generation.  Trigger it off the 21.6 kHz signal. 

4. Configure Counter 1 for continuous pulse train generation at, say 1 MHz.  This will be your app's master timebase.

5. Now here's the sneaky part.  Specify that Counter 0 use the output of Counter 1 as its timebase.  You'll need to use the DAQmx property nodes to get at this kind of detailed config.  Now, Counter 0's means for keeping time as it generates retriggerable pulses is based on the output of Counter 1.

6. You can configure Counter 1 to be pause triggered, so that it pauses when the enable signal is low.  When Counter 1 gets paused, Counter 0 will no longer see any timebase cycles, so it will be paused as well.  Thus your digital task will also be paused.

7. Be careful defining the pulse high and low times for Counter 0.  I would recommend you use units="Ticks".  If you know you are generating a 1 MHz timebase with Counter 1, then you need to make sure that the # high ticks plus the # low ticks is less than about 40.  (Because 40 microsec is a simple round number that's a bit less than 1 / 21.6 kHz)

-Kevin P.

[Nave]

Thanks for your help. This sounds doable! I'm going to try and implement this.

[Nave]

I've got a problem where turning on a digital output line stops my clock. It doesn't stop all my clocks, only counters 2 and 3. Coincidently I'm trying to turn on PFI 2 and PFI 3 when the clocks stop. I believe I got some setting incorrect. I've attached my task setup code. Any Ideas on what I'm doing wrong.

[Kevin_Price]

Many years ago, I recall a workaround under the legacy driver for cases where a digital task could interfere with a counter task in a similar way.  I don't recall whether it was the 6602 board or something else, and I don't believe I've encountered anything similar under DAQmx.   But in case it helps, it went like this:

On some boards, configuring the DIO port to output bits would perform some kind of internal reset on those pins.  If any of those pins were already in use as part of a counter task, the counter task could be affected (don't recall whether there was a DAQ error or whether the task silently started behaving differently).  The workaround was to configure the digital task first, then configure and start the counter task, and then go back and start the digital task.

On the 6602, counters 0 and 1 have dedicated pins that are NOT shared with DIO.  Counters 2-7 have to share.   Similarly, DIO 0-7 are not used by the counters, but DIO 8-31 are shared.  (Note: the DIO line # corresponds to the labeled PFI #).

Based on the code you posted, I wouldn't have suspected this problem, but it'd be worth a quick check anyway.  As part of troubleshooting, I'd recommend you avoid the "autostart" option on DAQmx Write.  You might also try to specify "one channel for all lines" in your Digital task config.

-Kevin P.

[Nave]

 It took me almost 2 weeks to get this setup, but everything is working just like I want it to. 

I did change a few things. LabVIEW wouldn't let me change the timebase for an individual counter. So I set the 1MHZ  pausauble clock as the master timebase for my Digital I/O card. Retriggerable pulse generation wasn't very practical for my application since I was pausing or never starting the 21.6KHz waveform. So I abandoned it and just used the actual pulse train signal as the sampling clock for my digital task.

Thanks for your help Kevin!

Message Edited by Nave on 04-11-2008 04:17 PM