01-31-2007 08:41 PM
02-01-2007 09:42 AM
I'm not near a LV machine right now, but will try to give this a look later on. Just letting you know you've "been heard..."
I haven't personally used the auto-increment feature, but *think* I have a fair-to-middling understanding of it. That said, I think that you *do* need to be configured as "retriggerable." The idea is that on subsequent triggers, the delay from trigger to the leading edge of your pulse will keep incrementing by the # of "ticks" you specify. If you then use that output pulse as an analog sampling clock, you may be able to characterize a well-behaved periodic signal despite drastic undersampling.
Suppose there's a 50 kHz sine wave coming in. You'd like to capture 20 samples per cycle in order to define a reasonably sinusoidal shape. The standard option would be to sample at 1 MHz and you'd collect 1 million samples per second. The samples would be spaced at 2 usec increments. Fine, but some boards can't handle it and/or you may not want that high a data rate to contend with.
If the sine wave is steady and regular, you can use the ETS / auto-increment feature to accomplish something equivalent with far fewer samples. All you need to do is make sure that each subsequent sample happens after an interval of (N * sinusoid period) + 2 usec. So you would setup your auto-increment to represent a time of 22 usec, or 42 usec, or 102 usec, or 1002 usec or...
Since real-world signals are often not rock-solid steady, a fairly reasonable first attempt would probably to go with (1 sinusoid period) + 1 usec = 22 usec. The more drastic undersampling is much more prone to trouble if the signal varies slightly or is simply not known with extreme precision. You'd accumulate phasing error over all the sinusoid cycles you're skipping.
-Kevin P.
02-01-2007 01:40 PM - edited 02-01-2007 01:40 PM
Message Edited by stilly32 on 02-01-2007 01:41 PM
02-03-2007 03:27 PM
02-05-2007 09:25 AM
Hi Snowman13,
What hardware are you using? Generally the fastest clock we have on our cards is a 80Mhz clock, which if I'm doing my math right should mean that the smallest increment you can use is 12.5 ns. So each time you will be incrementing in at least that time. If you keep the increment constant, you will never jump over an entire period of 25ns. Even if you keep the Auto Increment constant, you will be increasing your count each time. If you run the code I showed you with a constant Auto increment (use a large one for testing) and view it using an scope or the ai on your card (if you have it) you will see that over time the frequency of your pulse train will decrease.
Hope this helps,
Andrew S
02-05-2007 01:23 PM
...The only problem I am having now is that since the period of my sync is 25 ns, I dont want the delay procuced by the increment to exceed 25 ns, because once it reaches this point, it will skip over an entire period of my sync. So I would like to format the increment into a loop such that it starts back at zero after reaching a delay of 25 ns or so. Does anyone know of the most time-efficient way to accomplish this?
If I'm interpreting your post correctly, you may not be able to get there from here using the NI 80 MHz (12.5 nanosec) timebases.
In order to define these ETS pulses, you need to define both a 'delay time' and a 'pulse time' which correspond to 'low time' and 'high time' (or vice versa if you change the output polarity -- but I digress...). NI's counters require a MINIMUM of 2 timebases edges EACH for the delay and for the pulse for a total of 4.
You'd have a MINIMUM case of 25 nanosec delay followed by a 25 nanosec pulse. Next cycle would be a 37.5 nanosec delay followed by a 25 nanosec pulse. ALL of these cases would cause you to miss sync signals that are coming in every 25 nanosec.
Frankly, this is one heck of a requirement. If you need to generate a pulse inside each 25 nanosec window and you need the pulse to have a variable delay after each 25 nanosec sync signal, you're probably looking to vary by no more than 1 or 2 nanosec per cycle? Yikes! You need some hardware that's good to about 1 GHz! I'm afraid I don't know of anything to point you toward.
-Kevin P.
02-05-2007 09:40 PM - edited 02-05-2007 09:40 PM
Message Edited by snowman13 on 02-05-2007 09:42 PM
02-05-2007 09:44 PM
02-06-2007 08:53 AM
If you need to retrigger at 40 kHz, that's going to give you a much more manageable 25 usec rather than 25 nanosec between syncs.
It sounds like you (probably) will want to set this up using retriggerable single pulse generation. I myself just learned from stilly32's earlier reply that ETS variable-freq pulses can be generated without retriggering. I now would question whether the retriggered mode I used to think was necessary is actually supported at all.
If you use the mode shown by stilly32, about the only downside I see is that the phase of your 1st pulse relative to your 40 kHz sinusoid will be unpredicatable. But all the pulses thereafter should produce the right relative timing. Within a couple "apparent sinusoid cycles" worth of acq data, you can probably determine what that initial phase was.
Eventually, the ever-increasing delay involved in the ETS mode will overrun even a 25 usec interval, and you'll miss some cycles while you reconfigure. If you use the minimum increment of 12.5 nanosec, you'll get almost 2000 cycles of auto-incrementing delay -- but that still only represents 50 msec worth of data collection.
-Kevin P.
02-07-2007 01:21 PM - edited 02-07-2007 01:21 PM
Message Edited by stilly32 on 02-07-2007 01:23 PM