This is the answer to my own questions, it is working:
GLOBAL_INTERRUPT_STATUS_REG = 0x754, // One register on each TIO chip |size:32bit
---
GLOBAL_INTERRUPT_CONTROL_REG = 0x770, // One register on each TIO chip |size:32bit
enum GlobalInterruptControlRegBits
{
EnableInterrupts = (1 << 31), // For TIO(0) and TIO(1)
CascadeInterrupts = (1 << 29), // For TIO(0), cacade interrupts from TIO(1) through TIO(0)
};
---
INTERRUPT_ENABLE_REG = 0x92// for G0, for G1..G3 see RLPM page 3-18, 3-19
enum InterruptEnableRegBits
{
TCInterruptEnableG02 = (1 << 6), // for counter G0, G2, G4, G6, see RLPM page 3-18
TCInterruptEnableG13 = (1 << 9), // for counter G1, G3, G5, G7, see RLPM page 3-19
GateInterruptEnable
G02 = (1 << 8), // for counter G0, G2, G4, G6, not in RLPM
GateInterruptEnableG13 = (1 << 10), // for counter G1, G3, G5, G7, not in RLPM
};
---
STATUS_REG = 0x04 // for G0, for G1..G3 see RLPM page 3-28
enum StatusRegBits
// see RLPM page 3-28
{
assertsInt = (1 << 15),
TCStatus = (1 << 3), // bit03
GateIntStatus = (1 << 2), // bit02 Not in RLPM,
};
-------
InterruptAckReg = 0x04, // 0x004 (G0), 0x006 (G1), 0x104 (G2), 0x106 (G3) | Write-only | size:16bit
enum InterruptAckRegBits
// Not in RLPM
{
GateErrorConfirm = (1 << 5),
TCErrorConfirm = (1 << 6),
TCInterruptAck = (1 << 14),
GateInterruptAck = (1 << 15),
};
Have fun with it.