PCI 6602: Voltage Level and rising edge detection

[sauvageonne]

Hello,

First point Voltage detection:

I need to know with a PCI6602, how it detects a low level or a high level  when voltage applied is between 0.8 and 2 Volts.

When I applied a 1.7 Volts on a gate connection with a max internal clock on source, I saw like the counter saw level changed.

So, how PCI 6602 can see a rising edge when i applied a tension at 1.7 Volts with GND connected.

Second point Rising edge detection:

And When you used  the buffering semi-period measurement, you use internal clock on source and a signal on gate with variable duty cycle.

I need to know when you check each clock rising edge, if the gate is on high level the counter counts

if the gate is on low level the counter resets. But when you check the clock rising edge, if the gate is too on rising edge...

the counters counts or resets??? or no action from PCI6602??

[Kevin_Price]

1. A voltage level between 0.8 and 2.0 volts is really a no-man's land for TTL signals.  I'm not sure what the formal spec says, but in practice I'd expect undefined, unreliable, unpredictable behavior.  Such signal levels are not TTL-compatible.  Advice: condition the signal to make it TTL-compatible before presenting it to the counter gate.

2.  Buffered semi-period measurement is really more of an edge-driven than level-driven behavior.  It doesn't behave the way you described.  The count always increments with each Source edge, regardless of whether the gate signal is high or low.  On every edge, both rising and falling, of the gate signal, the count value is buffered and then reset to 0.  If you specify a "rising edge" polarity in semi-period measurement, it simply guarantees that the 1st value is buffered on a rising edge.  Thereafter, a value is buffered on every subsequent falling or rising edge. 

So the first value buffered is the time from starting the task until the 1st rising edge -- which is probably meaningless (as is typical in period and semiperiod measurements).  The next value buffered is the time between that rising edge and the next falling edge, i.e., the "high time" of the incoming gate signal.  The next value is the time between the falling edge and the next rising edge, i.e., the "low time" of the incoming gate.  Etc.

3. If a source edge is occurring at the same time as a gate edge, I think the result is a race condition in the board circuitry. Based on experience I'd say that you won't fail to count the source edge, but I don't know if it will be the last increment for the prior buffered semiperiod or the first increment for the next one. 

-Kevin P.