Precision with Multiple Counter/Timer cards and a DAQ

[spyrul]

Based on a previous question, but the circumstances have changed:

I need to generate up to 10 simultaneous TTL pulse train signals at up to 500 Hz with 0 to 100% duty cycles to open/close valves with a timing accuracy of 5 microseconds.  The pulse trains will be staggered with equal delays and begin with a single trigger. I need some DIO but I also need at least 4 AO and 8 AI.

i.e.: If you have a period of 40ms, and 8 valves, there will be a 5ms delay between each pulse train start. Each will have the same duty cycle and period.

The pulse trains have to be running simultaneously with a finite number of pulses.

Assuming 2 counters per valve for finite pulses, I'll need at least 20 timers.  My current plan is to use:

2 PCI-6602 (8 counters/timers each)

1 PCIe-6323 (4 counters/timers, 4 AO)

I see FPGA boards with well over 20 counter/timers, but I think FPGA might be out of my budget.

1) Is there a simpler/cheaper/more consolidated way to achieve this (20+ timers and AI/AO)?

2) Is it possible to sync all of this together and maintain the 5 microsecond accuracy with multiple boards?

[Kevin_Price]

I partly answered a different post, I'll focus here on different stuff.

A. The X-series boards (such as 6323) can generate finite pulse trains without pairing up counters.  So you can get 4 of 10 from that board alone.

B. Can you describe the exact nature of the finite-ness needed?   You've stated that they'll all have the same duty cycle and period, but need to be stagger-started.   Do they need to stagger-end as well?   Do each need to produce equal #'s of total pulses, do they just need the same end time, or can the durations vary widely?

C. You could save just a little bit by using a 6601 in place of one of the 6602's.  But honestly, I don't think it'd be worth it compared to the extra value / long term flexibility you get by having duplicate 6602's.

D. If the exact timing of all the pulses can be known prior to the entire finite sequence, this should be doable with the 6323 alone using its hardware-timed DO.  You just have to do some careful software processing to create a proper output buffer. 

-Kevin P

[John_P1]

I second Kevin's point "D", you should be able to use the digital output lines of a single 6323 to output all of your necessary pulses.  This board has 32 digital I/O lines which can output an arbitrary digital waveform using the internal clock at up to 1 MHz (giving a 1 us resolution).  You would just need to build the appropriate waveform in software.

Best Regards,

[spyrul]

Thanks.

Are there any examples that show how to generate (multiple) internally-timed DO pulses and/or combine DO pulses with counters?

I will most likely go with the PCI-6353.

[Kevin_Price]

Sorry, don't have time to track down specific examples, just have time for a quick reply.  This is actually an app that could make EXCELLENT use of a new feature on the X-series counters, one I spent 10 years whining about.  It's here now, and I'm looking forward to a chance to try it out.  The feature is the ability to perform hardwareware-timed variable-freq pulse trains via buffered counter output.

The working concept goes thisaway:

1. Define your initial digital states for all PWM bits(presumably all off).  Work out all your subsequent pulse transition times and make up a sequentially-ordered array of digital states at those times.  This will be the buffer you use for your DO task.

2. Define another array based on those transition times.  You'll need to make a buffered counter output task that will generate a clock edge (let's say rising) at each of those times.  I don't know the exact syntax as I haven't done it myself yet. 

3. The DO task should use the variably-timed output of the counter task as its clock.

The "beauty" of this method is that you can get microsecond-level resolution without having to define 1 million digital states per second of pulsing.  You only need to define the digital states when a transition happens, otherwise the previous state remains persistent.

The alternative approach would use a constant-rate clock to drive the DO task, but would take more SW work to define the buffer.

-Kevin P

[John_P1]

If you want to go with the DO option, the basic clocked digital output example can be found here.

The tricky part is to generate the desired waveform.  I think the attached VI should be pretty close to what you need to do this.  It's saved in LV 2010 but if you need it in another version let me know.

The counter option would also be nice, but unfortunately there are only 4 counters on X Series boards so you wouldn't have enough for your task with just a single board.

Best Regards,

[spyrul]

I'm running LabVIEW Professional 8.6 right now.

[John_P1]

Here it is in 8.6.

Best Regards,

[spyrul]

That's what I was looking for.  Thanks for your help.  Is that meant to control up to all 10 from one digital output?

[spyrul]

Oh, and can the sample rate be sufficient enough to achieve the 5 microsecond accuracy?