Problems retriggering

[DAK_Trap]

Greetings. I am using a PXI 6289 and I need to generate a fast continous pulse traing that is synced with an external clock. I have foudn several examples which at the core all have same base. Use a counter to generate a finite number of pulses that is trigered from the external clock and then retrigger it.

http://sine.ni.com/devzone/cda/epd/p/id/2415  Here is the most basic example.

So I have a 5kHz clock and I am putting it into the SRC of counter 0 (PFI8)

I use that as my trigger for CTR 0 output. I tell it to make a 50kHz clock and make 100pulses.

It does this well except when it goes to retirgger it misses one full cycle of the external clock. So the new pulse train is not continous. I have been looking through the posts and this should work. If you do 99 pulses you can see it does not miss a full cycle but the two clocks are no longer synched if you look at the signals on a scope.

In the end I jsut need to generate a fast clock from a slower clock and it needs to be continous. I would like it to work with the 6289 but I am beginning to open my mind to getting a new card if this doesn't work.

If anyone has any suggestions I would greatly appreciate it.

~D

[DAK_Trap]

Adding a few more notes:

I am using labView 8.2.1

Daqmx 8.3.0f3

[Paul_C.]

Hi Glish Lab,

The reason you are missing a full cycle of the external clock is likely due to the trigger rearm time on the PXI-6289.  I have a few questions as well as suggestions that might help us find a better solution for you. 

Do you know the accuracy of the 5kHz external clock?  I ask this because this would help us determine if you might be better off using a phase-locked loop (PLL) with the PXI backplane clock.  Depending on which PXI chassis you are using, the accuracy of the backplane clock might differ but is around +/- 25 PPM for the PXI 1042.  If your external clock is less accurate than the backplane clock, you might be better off bringing it in as a reference clock so that it will be PLL'd to the higher accuracy backplane clock. 

The only problem PLLing to the backplane clock is that they are only phase locked and not synchronized.  You will have to wait a few cycles of the 5kHz external clock for the backplane clock to fully PLL.  This also means to synchronize the two you will need to provide a digital pulse as a start trigger (after these few cycles) to synchronize the backplane clock.  You would then be able to divide down the backplane clock by an integer to adjust the sample clock to whatever you would like.  Regardless of whether the accuracy of your clock is greater or less than the backplane, you can still bring in the external sample clock as a reference clock (PLL'd to the backplane) and provide a digital pulse start trigger to gain a faster synchronized clock. 

If you could provide more information about the source of the external sample clock and details of the other devices you're using in your application, it might help me find a better solution. 

I hope this helps,
Paul C.

Message Edited by Paul C. on 10-25-2007 03:22 PM

[DAK_Trap]

Paul,

 I am not sure the accuracy fo the 5kHz clock. I will test that later today. For devloping this application I have been using an SRS15 MHz FGEN which has much less than 25ppm accuracy, but the clock I will actually use in the project will be less accurate.

In the end I need to generate a series of digital triggers that are synched with this 5kHz clock. So I planned to generate a fast clock fromt he 5kHz clock and use it as the digital output clock. Then my digital outputs should be synched to the original 5kHz clock.

In my hardware I was using a PXI6289 but I do have a 7811R on hand as well. I have tried doing this with FPGA and it has then same problem as the demo that I have been talking about. So I think what I am going to try this morning is going from generating a frequency pulse train to specifying clock ticks and make sure that it ends a little before so that it can be retirggered and as lock as the number of clock ticks is only a small percentage of the 50KHz frequency then it will not really be noticed too much in the digital signal. At least this is what I am hoping.

I am interested in the PLL solution becuase it does not require FPGA. Do you have any examples to get me started?

[Paul_C.]

Hi Glish Lab,

I'm afraid I mispoke.  I have since looked more into the specifications on the PXI backplane clock and it requires that the external clock that you provide be at 10 MHz.  I have been looking into the possibility of using a timing and synchronizations card to accomplish the same effect but haven't been able to verify if it is possible.  Could you provide a little more explanation of your complete applications.  In addition, could you describe what device is generating the 5 KHz clock.  Is there a limitation on the speed it can generate the clock?  The ideas you have with the FPGA sound good.  Let me know what the results of your test are.

Thanks,
Paul C.

[DAK_Trap]

Paul,

  I sucsesfully made a 50kHz signal from a 5kHz signal using an 7811R and LabVIEW FPGA. Basically the code looks for the rising edge of the 5kHz on one of the digial inputs. Then outputs 4 pulses at a rate of 50kHz. Then 1 half cycle at 50kHz and then last half cycle using clock ticks and I optimized the clock ticks so that the card would not miss a trigger. I then used this clock succesfully as the digial output clock of my 6289 and the digital outs are synched to the 5kHz clock. I used a digital start trigger for the digital output to ensure synchronization of the digital out the 5kHz.

This works pretty well. There is about 100ns of gitter, which I measured with an Oscope.