Thanks John, this did work.
However, I still encounter some problems and did not manage to implement or fully understand the clock issue. Therefore I've decided to leave it as an unsolved problem. As a workaround, I did the following: using a counter channel, I measured the frequency of the external clock. using this frequency, I can precisely determine when the analog output as described above is at an zero level and then close the gating. I don't like this workaround very much, because the external clock changes its frequency sometimes. But solving the problem correctly was simply to big a problem for my beginner's skills.
Thanks however for your ideas and help.
Peter
