When and how does the free running 40M Counter reset?

[pantani]

Hello LabView Friends,

I am using a cRio 9002 RT Controller with a 9101 FPGA Chassis and programming an VI for the FPGA target.

Now I would like to know the following points:

- What format is the free running 40MHz tick counter? What ist the maximum possible count?

-What happens if the maximum count is reached? Does it reset? How much time does it take?

-Or does it just start beginning with 0 without any reset time?

Thank you

marco

[TBalazs · Accepted solution]

Hello Marco,

by using any of the timing VIs for FPGA you can set the size of the internal counter to 8-Bit, 16-Bit or 32-Bit. This size value defines also the maximum possible count which is the maximum value that can be represented by this register.

There is no reset for this internal counter and it needs no additional time, as it is stated in the LV help for "Tick Count": A free running counter rolls over when the counter reaches the maximum of Size of Internal Counter specified in the configuration dialog box.

I hope this answers your question.

Best regards,

Blase