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[cRIO] Pulse width measurement

Hello,  I am working with cRIO-9074 with digial I/O module 9403. I was wondering where I could find examples or a list of function relevant to measuring the pulse width of a digital input (with resolution of about 10 usec).

 

- Thank you 

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Hey Ecw,

 

I great place to start would be IPNET.

 

It is a place where the community and NI post up examples. It's a very useful resource for FPGA examples.

Aashish M
CEO
TransferFi
www.transferfi.com
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Thank you,

 

At the moment I coded the pulse width measurement using a microsecond clock. I tested the frequency of FPGA cycles and got 75KHz (the while loop in the FPGA is running 75K times a second). Is this a reasonable/correct speed of the FPGA?

 

I am asking this because I don't know whether there is something I could enable or disable to make it faster. As far as I know there is only one 40MHz clock for the FPGA. There is no other options. However, I also noticed that even if I add more computation inside the while loop, the cycle frequency doesn't change, so I was wondering whether there is some configuration that set the cycle frequency to 75KHzand perhaps it could be set to run faster.

 

- Thanks

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Hey Ecw,

 

You'd want to make use of the Single Cycle Timed Loops (SCTL) in LabVIEW FPGA. If you refer to Pulse Width Modulation Example DAQ Personality, you'll see how the example uses SCTL to deterministically set the clock rate.

 

Hopefully this helps!!

Aashish M
CEO
TransferFi
www.transferfi.com
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I've implemented something similar using the example given above, however due to hardware limitations I'm unable to use the SCTL, this isn't too much of a problem as I simply use a while loop with a 4-tick loop timer, however when driven with a constant digital signal I get the pulse width measurements 'bouncing' between two values, it's not out by 1 or 2 ticks, it jumps around 1000 ticks, it also 'sticks' when I slowly ramp up the frequency, suddenly jumping to other values

 

any suggestions? I'm currently using the FPGA open function and accessing the FPGA in (I believe) scan mode, could this be the culprit? I've not undertaken the RT training course yet so I'd be poking in the dark a little

 

this is for a proof of concept demo in a few weeks time!

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