DownSample Counter in sync with Analog input!

[DSPGUY1]

Hi Otis,

I forgot to attach Vi before . Please find the attachment now.

Thanks

AM

[Otis]

For some reason the file did not attach, could you try attaching it again?

[Otis]

This example was meant to show essentially one thing.  How to take a clock, downsample the clock by creating 1 pulse for every N ticks, and then using the downsampled clock as the clock for another task (such as an Analog Input, Analog Output, or Correlated Digital measurement).

Since I didn't know if you had an external counter source, the top task creates a clock signal.

The middle task takes the output of the clock (or if using an ext clock, it would be connected to the Ctr1 Source Pin), downsamples the clock, and creates Ctr1 Output.

The bottom task takes the output and then uses the PFI lines for Ctr1 Out (PFI 13) as the sample clock source.  Now you have a downsampled signal.  As long as you referenced the downsampled clock (PFI 13) as the clock source, you can have multiple synchronized measurements based off of this clock.

If you have any other questions about the values necessary, take a look at the attached VI and look at the default values for the various controls.

Let me know if you have any further questions.

Regards,

[DSPGUY1]

Hi Otis,

Thanks for your prompt reply. After sending you last email I figured out the part of problem, which I was facing before. Now I see the counter output for top task using CTR0 out on BNC-2110 by hooking it to oscilloscope and then the middle task, which is downsampled by repeating the same procedure after disconnecting the first one.

Let us say I have 100 kHz pulse train generated by top task and if I divide it by 4 I can see 25 kHz on oscilloscope which is what I want.  BUT when I want to generate frequency at 200 kHz or 250 kHz by top counter and divide it by 4 in 2^nd counter I get 156.3 kHz output at the 2^nd counter. I think it is something related to internal clock. Could you please elaborate it to me?

The 2^nd part of my question is about analog input. Now when I acquire data I want it to be in sync with the outgoing counter output (which is 25 kHz from 2^nd counter).   I want something similar what we have in the example “ Multi-Function-Synch AI-AO.vi”. It might be already doing it in this Vi, if not how can I make it to do it.

I tried to attach the VI but something wrong. But this is same Vi, which you sent me. The setting for the parameters I chose is as under. Counter output is Dev1/freqout and downsampled counter output Dev1/ctro and source of downsampled ticks Dev1/frequency Output

I hope my questions are clear to you. I’ll be thankful for your help.

Regards,

 AM

[Otis]

Hi AM,

I'm not able to see the same behavior that you are seeing with the counters.  It could have something to do with 2 being the minimum number of down/up ticks that you can use.  Maybe make counter0 output 500kHz and then downsample by a factor of 8 and see if that does the trick.  Either way you are using an external clock in the final application, so it shouldn't matter too much either way.

Synchronizing Tasks:
I think this is one of the things that gets most typical DAQ users more confused than anything else.  Basically, if you want to make sure that your signals are synchronized, then all you have to do is use the same clock.

Synchronizing = Clock Sharing

It's really that simple.  This is true if you're synchronizing tasks, boards, or even cameras for NFL games to make the 1st down marker.

So in your case, you can just set up the AI and AO operations as you normally would, just make sure that as a clock source they both reference the same PFI line.  In the words of Emeril, "Bam!"  You're done, and your inputs and outputs are synchronized.

If you need more detailed information on Timing and Synchronization check this page out.

One last thing, since you are using Ctr0 to downsample your signal, then the source of the downsampled signal should be CTR0 Out and not freqout.  Other than that it sounds like you're on the right track.

[DSPGUY1]

Hi Otis,

I got a question, which is related to the ones I asked last time. You helped me to write a code that generates two counter outputs; the 2^nd one is count down by 4. Then I have to feed an AI signal using one of them as clock at PFI0. It works fine.  

 But now I have to generate one more clock that has to be in sync with the first one whereas 2nd counter output is already in sync with the first one. The third counter output is not possible in my case since I got PCI 6251, limited to two counter outputs. I want to know keeping the existing code in place how can I generate a sample clock for incoming signal at AI. The third clock should be in sync with first two and down count by some integer let say N. where N>>4.  It would be great if I can make this clock internal without using ctr outputs since I am already using ctro Out and ctr1 Out. I tried to attach the code but cannot do that. Please look at the example"737117 - Downsample Counter "you  sent me

Thanks a lot for your help,

AM

[Otis]

Unfortunately as long as you are using the PCI-6251 you will be limited to 2 counters. 

Originally you made it sound like the clock was coming from an external device and you wanted to downsample that clock to make your AI measurements.  Now it sounds like you are trying to generate the clock from the 6251.  If that's the case, then you should just do a timed AI Task like you normally would and not by trying to downsample clocks and route signals.

If you really do need to generate another clock though, there's no way to do that without getting a different or additional board.

[gus]

I have a couple more questions on this.

Are you using your analog output channels for anything?

It sounds now like you would like to have three signals generated.  Can you explicitly list what you would like them to be for me?  I'm not sure I'm clear on what the desired signals are and what the frequency you would like is (if possible).

gus....

[DSPGUY1]

Hi Otis,

Right now by using the attached code I can generate three different signals. Two counter output and one freq output. They all share the same source i.e. frequency output. The problem is I cannot generate 200 kHz at freq out, 50 kHz at ctr0 count down by 4 and some other frequency clock e.g. 8 kHz at cr1 but    I can generate 100 kHz at freq out, 25 kHz at ctr0 out and 4 kHz at crt1.

What I figured out the base clock for freq out is 100 kHz and 1 MHz. But I don’t understand why I get 625 KHZ signal when I wish to generate 200 kHz at frequency out. I am using  PCI 6251.

Could please help me on this . I'll be thankful.

AM

[DSPGUY1]

Hi Otis,

I tried ot attach code before  but did not work. Let me try this time.

AM