square wave down convert and synchronized AI AO!

[Otis]

Hi AM,

I think you'll find that the method that Gus hinted at will be the best for your application.  If you really need a 3rd counter then you could use the ao/SampleClock by creating a dummy AO Task that would then have the ao/SampleClock downsampled by the other counters.

The method that I originally recommended for you was because I thought you had an external clock source.  If you don't, then you could just create a normal AI operation, set the sample rates and make sure that it uses a start trigger to start when you start the other tasks.  I think this may be a case of us making a software version of a Rube Goldberg device.  You might want to take just a moment to step back from the whole scene and see what it is that you really need your code to perform.

Regards,

[DSPGUY1]

Hi Otis,

Thanks for your suggestions. I tried to get one output from ao but it did not work. I get some kind of nise on osciloscope instead of desired signal.

Let me try to reframe my problem. I want to generate three clock signal using PCI 6251 . They must have same source or time base. let us call first one as master clock at 200 khz. Now I want to count down the master clock by 4 to get another clock at 50 khz. Now I need another i.e third clock signal which is << master clock and is exact sub multiple of master clock , let us say 25. So my third clock is 8 khz( master clock is count down by 25).

I want to use 2nd clock as a carrier signal for FM  and want third clock to be used as an external clock  at PFI0 for a received signalwhich is 25khz modulatedand  is to be fed into ai channnel.

If you have any other suggestion pleae send it to me.

thanks

AM

[AnalogKid2DigitalMan]

DSPGUY1

Again, how about my suggestion from months ago:

If you know digital hardware, a standalone divide by 4 circuit is a quick and simple solution  for the 200Khz to 50Khz down-conversion.

You can extend this to get any divide by 2^nth subfrequency you desire.

Or, why not a DSP solution in hardware?

[gus]

I'm still not exactly clear on what your signals are, but take a look at the timing section in DAQmx Help >> NI-DAQmx Key Concepts >> Timing and Triggering >> Timing >> Clocks.  This has a diagram of the analog input timing engine.  As you can see in the diagram, the AI Sample Clock can be used to divide down an external signal if you provide that signal as the Sample Clock Timebase.  From your description it sounds like you have three signals you want to generate and the AI is the slowest of the three.  If this is true you can use the two counters to generate the "master clock" and div4 clocks and then use that signal as a sample clock timebase for AI and divide down there.

Let me know if I've missed something here.

gus....

[DSPGUY1]

Hi gus,

I tried to implement you suggestions but i could not do it. Either I did not understand exactly  what you asked me to do or  this thing does not support my application. I have attached my code. Could you please have a look on it and make changes like you suggested.

I know how to generate two counters  and now i need third clock either external or internal which is count down by some number e.g .25 from master clock  which is at crt1 out (The source for crt1 out and ctr0 out is ctr1internal output),  and sample the AI with this clock.

I want master clock e.g 200 khz, ctr 0 output at 50khz and third clock e.g 8 khz internal or external but msut be in sync with master clock.

I hope my query is cleat to you this time.

Thanks

AM

[Kevin_Price]

DSPGUY,

In the meantime, here's a really quick-and-dirty example to show you one way that can work.  I tested it on an M-series device with AO capabilities. 

Scheme:

1.  Generate master clock using the AO subsystem -- the AO sample clock.  I simply wrote 0V values to the output buffer b/c the actual output doesn't matter, only the sampling clock.  Note that the original default freq is 200 Hz so that UI indicators could show operation usefully, but it can also operate at 200 kHz.

2. Master clock is used as "Source of Ticks" for 2 counter pulsetrains.  They generate 50% duty cycle divided-down clocks that are sync'ed to the master clock.  The divide-down factors can vary independently.

3. Output of "clock 3" (your term from earlier in thread) is used to drive analog input.  It becomes the AI sample clock.

4. "Count" properties of each of the 4 tasks are continually queried in a loop so you can observe that all are functioning.

Try it out & see if this gets you going...

-Kevin P.

[DSPGUY1]

Kevin,

Thank you very much. I hope this would work. If I have any questions I'll let you know.

AM

[DSPGUY1]

Hi Kevin/ Otis,

I got the following error when I run the attached code on PCI –6120 and PCI 6052E.

“ Error – 89136 occurred at DAQmx start Task vi.

Problem reason(s): Specified route cannot be satisfied because, hardware does not support it.

Property: sampleclock.output Term

Destination: Device 1

Destination Terminal: PFI 0. “

But When I run it on PCI 6251 which a M series card. It works fine. I am using the code Kevin sent to me. I guess it is designed for M series cards only. I anyone of you can suggest me how t o optimize it for any NI card. It would be cool.

The problem is I work at two different places i.e. two different labs. I have PCI 6251 in one lab but got other two above-mentioned cards at the other lab.

Could you please help me to rectify this problem?

Thanks in advance.

AM

[DSPGUY1]

Hi Kevin/ Otis,

I got the following error when I run the attached code on PCI –6120 and PCI 6052E.

“ Error – 89136 occurred at DAQmx start Task vi.

Problem reason(s): Specified route cannot be satisfied because, hardware does not support it.

Property: sampleclock.output Term

Destination: Device 1

Destination Terminal: PFI 0. “

But When I run it on PCI 6251 which a M series card. It works fine. I am using the code Kevin sent to me. I guess it is designed for M series cards only. I anyone of you can suggest me how t o optimize it for any NI card. It would be cool.

The problem is I work at two different places i.e. two different labs. I have PCI 6251 in one lab but got other two above-mentioned cards at the other lab.

Could you please help me to rectify this problem?

Thanks in advance.

AM

[reddog]

What you're running into is differences between the routing functionality between devices built using the NI-STC ASIC and the NI-STC 2 ASIC.  The 6251 and all M Series boards are built using the NI-STC 2 ASIC, and the 6052 (and all E Series boards) and 6120 (and all current S Series boards) are built using the NI-STC ASIC.  The NI-STC 2 ASIC has considerably more routing capabilities than the previous version of the STC.  You can see this by looking at the Device Routes tab for each device within MAX.  Specifically, when exporting signals to PFI pins using the NI-STC, there is a dedicated signal per PFI pin that can be exported to that pin.  Again, you can see this by looking at the Device Routes tab in MAX.  You can also see this by looking at the Device Pinouts for your device.  On the pinouts diagram, each PFI pin also has the name of the signal that can be exported on that pin listed.  In your case, you're trying to export the ao/SampleClock signal to a PFI pin so you can only export it to PFI5.  Trying to export the ao/SampleClock to any other PFI pin will give you a route not possible error.  For the STC 2 based M Series devices, the same restrictions don't apply and you can export the signal to any PFI pin.  By exporting the signal to PFI5, your program should be able to run on all three of the boards without modification.

I also noticed one other issue you might run into with routing when trying to target the VI to the different hardware you mentioned.  On STC based boards, only the output from ctr0 can be used as a clock for other subsystems without external wiring.  Actually, the output from ctr1 can be used but it has to use pieces of ctr0 in order to achieve the routing.  Since you're using both counters, this will result in another reservation error.  To work around this, you will always need to use ctr0 to generate the clock for the analog input timing.