Piero:
You can try the following:
Set up one counter (ex. counter 1) for gated pulse train generation (pulse will output from counter 1 when gate is high); this is the pulse train that is going to be used as the gate for the buffered event (ex. counter 2). The gate for counter 1 is generated from the other counter (ex. counter 0). Counter 0 should be set for simple event counting with an initial count of 1 and set to count down. The source for this counter is the trigger signals (start and stop signals). When the start trigger comes in, the counter will count down to 0, the terminal count. When this happens, the output of the counter 0 toggles high, this then starts the pulse train generation. When the stop trigger comes in, the counter counts down to 2^n - 1, whe
re n is the resolution of the counter. This will toggle the output low again and stop the pulse train generation.
There are few things to note:
1)By default, the terminal count pulse will not appear on the I/O connector. You will need to call either Route Signal.vi LabVIEW from GPCTR n output to GPCTR n output, (n being the counter number) in order for the signal to appear.
2)frequency of the pulse train generated from counter 1 will control how fast you are doing buffered event counting on counter 2.
3) You will still need to poll counter 0 to check the current count, if the current count is less than or equpal to 2^n - 1, then you can stop all operations. Polling the current count of counter 0 should not affect the DMA buffering dramatically.
Hope this helps.
June
