what sets no.of pulses in 'finite pulse train' intermediate vi

[lalitha]

I want to know how the 'finite pulse train' intermediate vi works. from the VI info I find that counter n generates a continuous clock pulse and is gated by a gating signal coming from counetr n-1. but when I actually run this vi, I find that the counter 2 does not generate a continuous clock pulse and the gating signal is also not used at all for this vi.

I also find that the 'no. of pulses' input does not linearly correspond to the no. of pulses but to the speed of the motor as well. ( I am using the counter to generate a clock train that is used to drive a motor). Nevertheless, when I measure the freq from the output of the counter n , I still find it be to the same as the clock freq that I input thro
ugh my program (and hence independant of step pulses). This is surprising because the speed of the motor changes at constant freq clock trian from counter n.

can anyone tell me whats going on here ?


thanks very much,

Lalitha.

[Filipe A.]

Lalitha;

The VI you mentioned generates a finite pulse train using two counters. The chosen counter generates the finite pulse train on the default out pin. The gating counter controls or gates the chosen counter. This example uses counter pairs to determine the gating counter. The previous counter generates a single pulse that will gate the other counter which generates the pulse train. So, the pulse train generation will be "on" when the output pulse of the other counter is high, gating the pulse train generation counter.

I don't know how you motor works, however, since you are seing the correct number of pulses and frequency on the scope, that means the VI is doing what it is suppose to do. You need to figure out the transfer function in between the puls
e train that clocks the motor and its speed. Maybe, there is a scale factor in between those two parameters that is being overlooked.

Hope this helps.
Filipe A.
Applications Engineer
National Instruments

[lalitha]

Hello Filipe,

well, here's what I find when I run the vi. I am using a PC-TIO-10 board- so I have given the signals with ref to the pin outputs of this board as well.

I do not get a continuous clock pulse at the output of counter 'n' when I run the program with the gate of counter 'n' tied high all the time.

for instance, I tied gate 2 (pin 5) to high all the time and ran the program. I would have expected a continuous clock pulse to be generated at out 2 (pin 6 ). but only a finite clock pulse whose freq corresponded to the input clock freq was output at OUT 2.

then I tied gate 2 to low and repeated the run- again a finite clock pulse was obtained at OUT 2. It behaved as if the gating signal at gate 2 did not matter at all. All this was while
keeping the gate mode at 'count while high' and the pulse polarity at high (default values).

finally, I also wired out 1 (3) to gate 2 (5) and ran the vi. this is exactly the way the I/O connections should be made as per the vi info. but there was no output at OUT 2 (6) even though the gating signal was observed at OUT 1 and therfore tied to gate 2.

thus my VI is not generating a continous clock pulse at the counter 'n' OUT pin - I always get only a finite clock train and this is regardless of whether the gate of the counter 'n' is tied to high/ low/ OUT of previous counter.

why does this happen ?

thank you
Lalitha.

[lalitha]

hi Filipe

I have tested the program again and found the trouble. Now I understand how it works, thanks very much.

Lalitha.