CRIO 9401 output has offset

[pk_crl]

iam trying to output pulse via CRIO 9401  .

when the  pulse has 10% duty cycle the output is correct with vmin 0 volt and vmax 4.2 Volt. But, when the pulse has 50% duty cycle the output is drifted with vmin -2Volt and vmax 2volt. what is the reason for this drift in the output when on time period equals the off time period. iam checking my output in tektronix CRO.

The block digram is attached.

[MeghanK]

I would suggest reading the following KnowledgeBase to verify that you have everything setup correctly for the DIO lines in LabVIEW FPGA.  It doesn't seem right that your duty cycle would affect the output voltage. If everything is setup according to this document, let me know.  Thanks!

Why Won't My cRIO 940x DIO Module Produce the Correct Output Value?

[pk_crl]

Thanks Meghan for your reply. I have set DIO 0:3 as output and DIO 4:7 as input already. But yet , the problem persist. I have attached my code here.

[MeghanK]

No problem.  I could not find your attached code, could you try reattaching it?  Thanks!

[pk_crl]

Here is my code.

[MeghanK]

What are the output values at duty cycles other than 10% or 50%?  Is it only the duty cycle of 50% which causes the error in output voltage?  I would suggest using the attached FPGA VI written for PWM Output with FPGA, to see if you can reproduce the results.  Let me know how it works out, thanks!