11-30-2013 08:19 PM - edited 11-30-2013 08:20 PM
Hello ,
I am using 9201module for 5 current(ACS758 sensor) and 3 voltage souces sensing and 9401 for PWM output with cRIO 9012, the problem is when i start the VI not the gating signals the current values are accurate and when i start the gating signals also the current values are changed, i am not able to figure out the problem please help me in this regard.
Kudos and others i thanx u peaple in advance..
VI is attached.
Regards,
azy
12-02-2013 08:04 AM
Hi Azy,
What do you mean by the current values change? By how much?
Of course switching the DIOs could lead to increased power consumption of the cRIO. Does it have its own power supply or is it somehow connected to whatever you measure.
Kind regards
Heinz
12-02-2013 09:30 AM
Hallo Heinz,
I thank you for the reply, in my board i have five of these sensors(ACS758) and i using Siemens 24V/5A power supply which is connected to cRIO and the same power supply goes to the board which has one +5v and one +12v regulator , +12v for 4 gate driver IC's(IRS2186) and +5v for the 4 temperature sensors(MCP9700) and 5 current sensors(ACS758). Is it enough?
and secondly i want some guidance regarding the Host VI, not enough experience with Hst VI, could you please help me that which functions can i perform from those VI's using Host VI to save FPGA resources and for calculation of offset and current calculations(right now i do these in FPGA VI) and how to make a Host VI??
Thanx in advance!
Regards,
azy
12-02-2013 07:22 PM
there are many issues with the code you posted. you need to review some of the examples of BLDC motor control or inverter control to see better/suggested ways to do what you are trying to do.
12-05-2013 05:33 AM
Hi Azy,
sorry for the late answer.
The Power source is definately enough to power the RIO. But still I don't know what you are measuring and how "gating the signals" influences your board. Are you sure the increased current is not expected?
I guess by Host VI Real Time Target VI. This what you usually use to save FPGA resources. The Host VI is the VI on your Desktop PC. Usually you transfer data from FPGA to RealTime-Target by DMA-FIFOs. I gathered you some getting started links, but I would advise you to take a FPGA and RealTime Course.
RT to Host Communication
http://digital.ni.com/public.nsf/allkb/48D244EC86971D3986256BD4005CCC28
DMA FIFO
http://www.ni.com/white-paper/4534/en/
I hope this helps,
Kind regards