FPGA IP integration

[Mejdi]

Hello,
I'm trying to add a VHDL IP to an FPGA project in simulation mode,
But none of outputs are moving

Any help?

[eaguero]

Hi Mejdi

I think this is a good guide to follow:

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA03q000000x0jiCAA&l=en-US

Please let me know if it is useful for you

[Mejdi]

Thank you for your response
My problem is not addin an IP but simulating it in simulation mode.
I noticied that when i use IP with no clock and reset it works, but when I add clock and reset nothing works.

[eaguero]

Mejdi

In this link are written all the requirements for simulation mode.

https://www.ni.com/docs/en-US/bundle/labview-fpga-module/page/preparing-ip-for-use-with-the-ip-integ...

Thank you