Is there a way to check the status of a single bit while reading data in on an external clock?

[nlthomas]

My Task:
I am using the PCI-6533 DAQ card for Digital buffer Pattern input to a binary file. I need to sample the data (8 bits on port1) on the rising edge of an external read clock if and only if another bit, lets call it DBK, from the external device is low.

Where I am at:
I am currenly using a program/vi that is very, very similar to the example program entitled "Bufferd pattern input.vi." I am reading the data properly on the rising clock edge to the file and have confirmed that it is correct.

My Problem:
I want to continuously check the status of the bit mentioned earlier, the DBK. Right now, I am ignoring this signal. I want to read the data like I current
ly am when DBK is low. However, when DBK goes high, I need to make a note of that in my binary file. (Just a note: There will not be any read clock signals while the DBK line is high) I will then wait to read data until the DBK goes low again.

Basically:
I need to make a mark in my binary file on the rising edge of DBK... How do I find this rising edge if I am already using the REQ1 (read Clock is currently attached here) line of my DAQ card.

I could use any suggestions that you might have.
Thanks,
-Nathan

[rgharrison]

Hi Nathan,

Since you have to monitor the state of a line (DBK), you will have to process each sample to determine the state of the line before writing the buffer to file.

What I propose is that you acquire your data buffer and use a bit mask to determine the state of your specific line. Assuming you are reading 8 bits and your DBK is the 3rd bit, I would "And" each sample of your buffer using a for loop with "00000100". This will allow you to quickly check for a 1 or 0 in that bit position. Depending on what you determine, you can write an extra bit to the file which marks when this value is high or low.

In other words, the only way you can accomplish this task is to process each sample of your acquisition and determine if the bit is high.

Hope t
hat helps. Have a good day.

Ron

[nlthomas]

Hi Ron,

Thank you for your comment. I think that I may have led you a little astray but I think that I can use your solution. Let me know if you think that the following will work.

I have port 0 (not port 1) reading in 8 bits of data. The DBK line is not part of that 8 bits. Using your solution, it sounds that I will have to sample (read in) a second port and monitor that line at the same time so that I would be reading in 16 bits but only using 8 of them. Would this work?

However, I am not certain that will work because my DBK line goes high on the falling edge of my read clock (Not on every read clock; after about 2000 read clocks) and I will not get any more read clocks after the DBK goes high until after the DBK goes low again.
To make t
his a little less confusing: When sampling on the rising edge of the external read clock, I will never see the DBK go high or low, it happens between two rising edges. The external read is approximately 6 KHz or every 170 micro-seconds except when there is an "active" DBK then there may several mili-seconds between the rising edges of the clock pulse. -> Therefore, I do not think that your solution will help me... What do you think about the following...

My next attempt at a solution:
Do you think that I will be able to use multithreading in my application so that the first thread will do what I already have done (i.e. just read the data to a buffer/file on the rising edge) and set the second thread up to "timeout" when it hasn't received a read clock in say 20 microseconds (The DBK has a minimim time that is greater than this.) When I receive this timeout, I write a "mark" in my file then start looking for a read clock again. Do you think that this is a feasible solution? D
o you have any other suggestions?

Thanks again.
-Nathan

[rgharrison]

Hi Nathan,

If you are not using the second group on your 6534 board you can use this for your DBK signal. What you would do is read in a port of 8 lines in your second group and you would configure this group independantly than your first group. You would still use an external clock to clock your DBK but you can set it to read on the falling edge of your Read Clock instead of the rising edge as in your first 8 lines in group 1.

The short is that you configure two groups independantly and sample one on the rising edge and one on the falling edge. As for your solution, if your DBK occurs every 20us then your solution with the second thread could work. Although since you are using software timing it could be off (especially at 20us).


What I am curious about is why your DBK signal can not be seen if you sample it on the same edge as your data. Is it the same width or shorter than your Read Clock? Anyway, my suggestion above might do the trick. Well, good luck.

Ron

[nlthomas]

Hi Ron,

Thanks for your help again. The DBK signal is very inconsistant compared to the read clock. The data on the tapes are placed on the tape in blocks. The blocks can range from 6 bytes to 2024 bytes. The DBK signal represents the datablock and is active during the "break" or "gap." The reason that I can not sample the dbk with the data on the read clock is that the DBK goes active on the falling edge (I am reading data on the rising edge) and goes inactive before the next read clock. The "gap" may last 20 us or it may last 10 us. It doesn't really matter the read clock will still not go active during an active DBK.

I tried what I wrote before and found that the software timing was too slow to catch the DBK signals. I wil
l try to capture the third port (where I have my DBK pin attached) on the falling edge of the read clock. I really don't know if this will work or not either. The DBK goes high at the exact same time as the read clock goes low, so I may still miss the DBK signal. However, I can try to use the falling edge as a start trigger and take say 5 samples and if any of the DBK samples are high, I could consider this an active DBK.

Do you think this will work? I assume that I would have to attach my read clock to both REQ1 (like it is currently) and to the start trigger on my PCI 6533 board? Does anyone know how to implement something like this? While I have to use multithreading i.e. two while loops, One like I already have to capture the data, the other to capture the DBK?

Thank you so much for your time.
-Nathan

[rgharrison]

Hi Nathan,

I had another thought. You could configure the board for change detection. This means data will be clocked whenever a digital line changes on the port. However, you can choose to only configure change detection on 2 lines, your clock line and your DBK line. This means that your clock signal will cause the DAQ board to sample every time the clock changes states. Similarly, it will clock in data everytime the DBK changes values as well. You can simply discard any sample you are not interested (for example high-to-low transition of your clock signal or your DBK). I think this option might work. One of the keys to this mode is that it uses interrupt based transfer instead of DMA transfer.

Have you tried har
dware timed input? Using an internal clock and a rate fast enough to catch the DBK?

Anyway, hope that helps.

Ron