Hey Jamie,
A couple thoughts, by default, pattern input will export the REQ clock. In contrast, by default, pattern output will import the REQ clock. This should explain your haywire behaviour when you run pattern input before pattern output.
What I would do now is create a bare-bones program. Configure port A for analog input, configure port C for analog output and connect all 8 data lines and the REQ lines. Then start the output operation (which will wait for the external clock) and then start the input which will automatically export the internal clock to the output operation. This will test just the data. Don't include the other ports or the triggers. Keep the rates low for testing purposes. If it pa
sses, continually increase the rate. If it continues to work, slowly add the triggers. Eventually, you will find a piece of code that you add that breaks the program.
If you keep you digital rates low, you shouldn't be affected by noise too much. Once you start increasing your rates, you will notice that noise might start affecting the data. To overcome this noise, twist a grounded wire around your data lines. This will minimize the crosstalk on the signal lines.
This should be the most minimal test of communication between two independently operation ports. Hopefully this works out. If it doesn't, try the other card.
Ron