12-03-2014 02:25 PM
Hello! The application I'm going to develop must do the following:
What concept would you advice me to use in such application if I have LabVIEW 2013 SP1, cDAQ-9188 chassis and NI-9402 digital I/O module (I can't use "Wait for next sample.vi" according to the help I read, for example)?
Any comment will be appreciated!
12-04-2014 05:59 AM
So, in order to clarify what do I mean about concept, I decided to add this self-reply. I tried to use HW timing for my digital output, which is, according to the DAQmx Help, supported by my combination of devices, and received Error -200077 (see attached picture for details).
Is it something I have understood wrong in DAQmx Help, or there is actually a contradiction?
And, after all, if I can't use HW timing for my task - with what kind of approach may I implement (if any) to guarantee duration of my outputs?
12-04-2014
07:15 AM
- last edited on
10-11-2024
05:48 PM
by
Content Cleaner
Dear kpnk,
of cause you can use HW timing but the "Hardware-Timed Single Point" is a very Sampling Mode for deterministic RT applications and is also just supported by advanced DAQ hardware you can see here.
Does My DAQ Device Support Hardware-Timed Single Point Sampling Mode?
What you need is a simple continues edge counting which is controlled by a Gate to activate and deactivate the counting.
In this Getting Started document is described in details and how to implement it.
Using Duplicate Count Prevention for Counter Tasks in NI-DAQmx
Kind Regards,
SG3 | Applications Engineering | National Instruments | NIG |
12-05-2014 07:26 AM
@SG3 wrote:
What you need is a simple continues edge counting which is controlled by a Gate to activate and deactivate the counting.
In this Getting Started document is described in details and how to implement it.
Using Duplicate Count Prevention for Counter Tasks in NI-DAQmx
Kind Regards,
SG3 | Applications Engineering | National Instruments | NIG |
Dear SG3, thank you very much for your reply! I will try to implement this approach and will keep this thread updated.
12-08-2014
12:56 PM
- last edited on
10-11-2024
05:48 PM
by
Content Cleaner
Dear SG3, I constructed two VIs for my aims, one is based on this duplicate count prevention feature you forwarded me to. Since I have not found any example VI (just a flowchart), I attach the one with my comments. Do you think, that I have understood everything right? The idea is, again, to count edges only when a gate at the device is enabled (and I think, for this reason, one have to deal with the gate terminal of the counter channel I use).
Second VI (also attached) was based on this example and was modified by me in order to enable a single digital line with a period set at "Sample Clock Rate" for "Amount of pulses" times is a row - this is for enabling a gate of the device itself.
Now I want to merge this two VI's to fulfill simultaneously all my needs - to enable the gate at the device and to enable edge counting from the device at the same HW-timed period of time (and all this - many times one after another).
Do you think, that my way by now doesn't lead to nowhere? By now I have obvious troubles of writing digital output (second VI) while trying to count edges (first VI) - the error is that one can not use a terminal which is already reserved for another task.
I have somehow a feeling, that I am doing something either too complicated while there is a simple solution, or something completely wrong.
12-19-2014 04:10 AM
A fruitful continuation of this thread is here (for anybody who will be probably interested in future).