Hi Vishal,
I partially answered this question in your previous post:
http://exchange.ni.com/servlet/ProcessRequest?RHIVEID=101&RPAGEID=135&HFORCEKWTID=77617:5&HOID=50650000000800000086A80000&HExpertOnly=&UCATEGORY_0=_31_%24_12_&UCATEGORY_S=0
You should change the REQ & ACK polarities in the Handshaking Parameters of the DIO Config.vi. The CPULL is only used to configure your control lines at startup. If CPULL is high, then all your control lines (REQ, ACK etc.) will be high and vice-versa for if CPULL is low at startup.
If you are using Burst Mode, check out example Burst Mode Input.vi. The PCLK value will be the burst delay amount but you must make sure to change one the handshaking parameters to get this to work correctly. You must change the "Ackno
wledge Modify Mode" to be "delay". Then it will work correctly.
All the ground lines in the 653x are connected together internally and grounded to earth through the computer ground. You can use any ground with any signal. It is typical to use the ground next to the pin for maximum noise protection.
You are correct that the handshaking parameters in pattern I/O will only decide the rising/falling edge for the REQ signal. The edge mode is ignored in pattern I/O.
Hope that helps. Have a good day.
Ron