Hello,
We hooked up the 6562 to another device and I was able to output signal through PFI 1, PFI 2 using markers in a script. I also was able to generate data to channels 0-15. And the result was great (gave a amplitude of 300 mv).
The only problem is that I was exporting on board clock signal to the DDC CLK OUT(LVDS) channel in the front panel DDC connector, the amplitude is only 50 mv). The code I ran was exactly like the one given in DynamicGenerationWithExportedClocks.c
ViReal64 sampleClockRate = 50.0e6;
ViConstString sampleClockOutputTerminal = NIHSDIO_VAL_DDC_CLK_OUT_STR;
/* Configure clocking parameters */
niHSDIO_ConfigureSampleClock(vi, NIHSDIO_VAL_ON_BOARD_CLOCK_STR, sampleClockRate);
/* Configure clocks for export */
niHSDIO_ExportSignal(vi, NIHSDIO_VAL_SAMPLE_CLOCK, VI_NULL, sampleClockOutputTerminal);
/* Un-export clock */
niHSDIO_ExportSignal(vi, NIHSDIO_VAL_SAMPLE_CLOCK, VI_NULL, VI_NULL);
I am wondering if there is anyway to increase the amplitude of the DDC CLK OUT output? Thank you.