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Ni 6562 PFI clock

Hello,
 
We hooked up the 6562 to another device and I was able to output signal through PFI 1, PFI 2 using markers in a script. I also was able to generate data to channels 0-15. And the result was great (gave a amplitude of 300 mv).
The only problem is that I was exporting on board clock signal to the DDC CLK OUT(LVDS) channel in the front panel DDC connector, the amplitude is only 50 mv). The code I ran was exactly like the one given in DynamicGenerationWithExportedClocks.c
 
ViReal64 sampleClockRate = 50.0e6;
ViConstString sampleClockOutputTerminal = NIHSDIO_VAL_DDC_CLK_OUT_STR;
 
/* Configure clocking parameters */
niHSDIO_ConfigureSampleClock(vi, NIHSDIO_VAL_ON_BOARD_CLOCK_STR, sampleClockRate);
 
/* Configure clocks for export */
niHSDIO_ExportSignal(vi, NIHSDIO_VAL_SAMPLE_CLOCK, VI_NULL, sampleClockOutputTerminal);
 
/* Un-export clock */
niHSDIO_ExportSignal(vi, NIHSDIO_VAL_SAMPLE_CLOCK, VI_NULL, VI_NULL);
 
I am wondering if there is anyway to increase the amplitude of the DDC CLK OUT output? Thank you.
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Tim,

If you have a 100ohm resitance between the two polarities of DDC CLK OUT LVDS and you properly export the signal to that terminal in software (ie send it to the DDC instead of the SMB terminal) then the signal should be >250mV.  If you have significant cabling in excess to the SHC cable then you could be introducing loss into the system that could decrease that amplitude.  A 50mV swing, though, indicates a significant amount of loss.  If you connect the DDC CLKOUT LVDS signal to only a 100ohm resistor, is the swing still only 50mV?

Message Edited by Ryan M on 12-04-2006 02:47 PM

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Yes, we tried 2 different cable and we connected the DDC CLKOUT LVDS signal to only a 100ohm resistor. The swing is still only 50mV. However, PFI 1 PFI2 and the data in channels 0-15 are all >300mV.
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Tim,

How about DDC CLKOUT LVPECL, do you see a signal swing on that channel?  This is an LVPECL output so the levels wont be TIA-644 compliant but may give some insight into the problem.
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