I am clocking a device at 3.2 MHz. This device outputs analog information on both edges of the 3.2 MHz clock (6.4 MHz). I am using a PCI-6534 to generate the device clock (3.2 MHz) and a sample clock (6.4 MHz). I am running the PCI-6534 at 12.8 MHz so that I have better resolution. In other words, I can place my sample clock within 1/2 intervals of the output period. I would like to do better than this. If I could, I would output patterns at 25.6 or even 51.2 MHz. Unfortunately, the PCI-6534's maximum output rate is 20 MHz. By using an even faster clock, I would be able to place the sample clock within an even smaller interval within the output. My output does not change instaneously and this is why I would like to have
flexible placement of the sample clock. Any ideas? I am using the PCI-6115 high speed A/D converter.
