Pause Triger on PCIe-6537 card

[BPW]

I am currenlty using the PCIe-6537 card to capture data, it is configured for external pipeline clocking as I want to use the pause trigger functionalitly.  The problem I have is that when the pause trigger frequency matches that of the external clock ,I am double triggering on the data, ie capturing two bytes(of Identical data) where I expect only one.  The help that I have read on using the pause trigger suggests that it takes one clock cycle to pause the triggering, does this explain the reason for the double triggering.  If it does, is there any way round it.

Cheers

Brian

[Robert_Lee_NIUK]

Hi Brian,

I would agree with you that the double triggering is occurring because the pause trigger takes one cycle to 'pause'. I am going to have a chat with some of my colleagues and see if they can postulate a possible solution for you. The trouble is that because PCIe is so new, there isn't much information on this kind of thing happening. It's almost as if the express bus is opporating too quickly! However, I am sure there may be a work around so when I have more information I will get back to you.

Best wishes

[Robert_Lee_NIUK]

Hi Brian,

I've been having a chat with a colleague who works in the High Speed Digital IO team, and I think we may have at least one possible theory on the behaviour you're experiencing. When in pipelining mode, which is the best sampling mode for your type of acquisition, you need to ensure that you provide a large enough setup and hold time on your pause trigger. These values are documented in your device specifications which, for the PCIe-6537, are stated as
                                 PCIe
Minimum
provided hold
time with                   1.1 ns
respect to PFI 4
(tPH)

Minimum
provided setup
time with                    Sample clock interval (tP) 5 ns 
respect to PFI 4
(tPSU)


tP is the Sample clock interval; Values assume the sample is generated and acquired on the same clock edge. Includes maximum channel-tochannel skew. Valid for all data and events.


So if you are pause triggering at the exact same frequency as you sample clock, it could be that there is not enough setup or hold time being allocated for the pause trigger to work efficiently.

Setup and Hold Times

When a DAQ device samples a digital signal, the signal must remain stable for a period of time before and after the assertion of the clock edge used for timing. The amount of time before the assertion of the clock is called the setup time. The amount of time after the assertion of the clock edge is called the hold time. Refer to your device documentation for minimum setup and hold times.

I'm trying to figure this out in my head, but could do with some more information about the specific signal that you are sampling when the pause trigger goes high. It could be a combination of factors which are causing two samples to be received, but with further information, hopefully we can narrow this down.

Best wishes

Message Edited by Rob L on 10-10-2007 06:02 AM

[BPW]

Hi Rob

Thanks very much for your input, it appears there is a problem with the timing/edges of the clock, strobe and data.  This is now being addressed by the hardware design team and initial results are promising.  I think we can consider this investigation closed for the present time.

Cheers

Brian

[Robert_Lee_NIUK]

Ok Brian,

Many thanks for letting me know.

All the best