Routing Sample Clock

[digitalIO]

Hi,

I am wondering whether it's possible to internally route the sample clock of a 6534 to any of the 32 DIO channels. I know that I can route it to the PFI pins, but the system I am working on currently does not allow physical access to any pins except the 32 DIO pins. I am working in LabVIEW 7.1 with NI DAQmx 7.4. Any advice?

Thanks!

Kevin Norman

[Jordan_D]

Hi Kevin,

Internally routing the sample clock to the DIO channels is not possible using your 6534. Perhaps if you told me a little bit more about your application I might be able to come up with some way to help.

[digitalIO]

Thanks for the reply.

I'm trying to develop a serial interface to communicate with a UUT. One of the lines to the UUT is a clock signal at a precise frequency which controls the data transfer. From the example code I have been analyzing, I believe if I just make one of my output waveforms alternating true and false I will have essentially the clock signal needed on one of the DIO pins. What do you think? If there's not a simple solution, it is possible to dismantle some of the legacy hardware to get at the other pins from the card. I'd rather not if I can avoid it.

Thanks again,

Kevin

[User002]

Your idea of using a pin as a clock is a good one, but you really want to do False/True, not True/False, so you put the clock edge in the middle of the data and not at the same time as the data transition.  For example:

Data:   D1    D1   D2   D2   D3   D3
Clk:     F       T     F     T      F     T

Note how the data is stable before and after the transition from False (0) to True (1).  That will give a reliable data transfer.

[Jordan_D]

Hi Kevin,

Using the setup that you described, you will be limited to outputting half of the frequency of the clock signal. If you route through the counter you will have to divide down the source and if you route through the digital output, you will only be able to toggle the output up and down on every other clock edge thus dividing your frequency in half again.

[digitalIO]

Thanks for your reply.

My system does not use a very high clock frequency (~40kHz), so this is not really an issue. I did manage to get access to the PFI lines off the card and was able to export the clock to PFI 2. I was surprised that the clock is only a short pulse (~50ns). I believe my system needs a clock with 50% duty cycle. Can this be achieved with the internal clock, or should I stick with my previous method?

Here's the timing diagram I'm trying to implement:




Thanks for all the help!

Kevin

[digitalIO]

Sorry, that pic didn't work.

Let's try again

Message Edited by digitalIO on 07-26-2007 12:50 PM

[User002]

When you looked at the other connector, you probably saw the internal 20 MHz clock (50 ns) that was routed out.  That connector only offers you the choice of 20 MHz in, so your card will be on the same clock as others, or out so the other cards would be on the same clock as yours.  You should probably just go with pattern replication out the main connector instead of trying to get what you need out of the other.

If you try your pattern that uses one bit as the clock, replicates the data, and output it at 86356 Hz, you should be able to create the timing you show (1X).  Remember, the 100 ns setup time is a minimum, so you can set up the signal one pattern before the clock edge.  Same for the 100 ns hold time -- just hold the pattern one longer.  Here's a 4-bit example:

0    1    0    1    0    1    0    1    0    1    0    1      clock pattern bit

x     x    d1  d1  d2  d2  d3  d3  d4  d4  x    x      data pattern bit

0    0    1    1    1    1    1    1    1    1    1    0      enable pattern bit

If your timing needs to be more exact, just increase the frequency and increase the number of times the pattern is replicated (while fine-tuning the exact amount).  For instance, if the setup or hold time needs to be less than 1/2 clock, you could double the output clock frequency again, replicate the clock pattern (like the data in the example), replicate each data pattern four times, and then place the edges of the enable pattern as required.  You'll definitely want the final output pattern in an array before you try to send it, or you might run into throughput problems with your system if you try to create the three bits during a single output clock period.

Good Luck!
David

[VadimZ]

Hey ya'll.

I am trying to create the same pattern using a PCMCIA 6024E Card. Is it possible for you to post the used VI.

Thanx

[Jordan_D]

Hi VadimZ,

The PCMCIA 6024E card does not support hardware timed digital output. Software timed digital output is your only option.

If you are new to LabVIEW/DAQmx, you might want to take a look at the following example programs in the LabVIEW Example Finder (Help»Find Examples)

Hardware Input and Output » DAQmx » Digital Generation » Write Dig Chan.vi
Hardware Input and Output » DAQmx » Digital Generation » Write Dig Port.vi

Message Edited by Jordan D on 10-23-2007 11:36 AM