Sync multiple cRIO chassis via 9401 DIO issues

[Acmoya]

Hello all,

Hopefully someone can help me.  I am attempting to sync the acquisition of DSA modules across two cRIOS via a digital pulse output / input.  I have one Master cRIO which outputs a digital signal based on a desired pulse width which then triggers the acquisition of the 9234 modules.  The master cRIO output the digital signal fine which I verified with a multimeter.  The problem is that the slave chassis never sees the digital input.  I have the output wired from DIO 0 on the master to DIO 0 on the slave.  Each module is configure for the correct line direction, but I still only read 0 on the slave module.  The fpga on the master and slave are identical except one generates the "clock" and outputs via the 9401 while the slave module waits for the "clock" or falling edge on the digital signal.  To check this, I write the clock boolean to a FIFO which I plot on my Host PC.  Is this the correct approach?

Any help is greatly appreciated.

Thank You

-Adam Moya

[preston_johnson]

syncrhonizing DSA across cRIO chassis is difficult.  To truly sync them you need to share the oversample clock, or since this is not reliable over the 9401 / 9402.  The 9401 is not fast enough to source the oversample clock, the 9402 is.  However, for DSA to work well, a very high precision oscillator must be used, and neither the 9401 or 9402 are accurate enough. 

What we have done in multi-chassis DSA apps in the past is to pass say a 1kHz signal and use the resampling functions (found in the following dev zone document) to re-align the data to the 1kHz reference clock generated and shared by the 9401/9402. 

http://zone.ni.com/devzone/cda/epd/p/id/6146 

Try the above app - it should get you moving along quickly.  I have attached additional resources for DMAing the signals to the RT controller and sample applications for managing, logging, communications, etc with DSA. 

[Acmoya]

Thank You Preston,

I had previously seen your example, but had trouble compililng the fpga code due to insuffecient memory when maxing out the channels.  I tried simplifying this down and used a combination of your suggested code and the code found here:

http://www.ni.com/white-paper/4217/en 

I also created a different code for each master and slave fpga, but think your idea of one code splitting the inputs / outputs on each 9401 module is easier.  I am going to try this again today and see if I have any luck.

Thanks for the info

-Adam Moya

Sandia National Laboratory

National Solar Thermal Test Facility

[preston_johnson]

Thanks for the reply, Adam. 

The second example you reference is for Successive Approximation ADC boards (SAR) - like the 9215.  DSA boards like the 9234 require precision clocking using their own on board clocks. 

To better understand how their analog input code should work on the FPGA, you may want to look at the cRIO Wavefrom Reference design.  While this does not syncrhonize, it is the basis for the sync example I pointed to. 

https://forums.ni.com/t5/Example-Code/Reference-Application-for-NI-CompactRIO-Waveform-Acquisition/t...

Preston