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sample clock enable/disable on LVDS board PXI-6561?

I'm trying to decide if the PXI-6561 board will work for my specific application and have a few questions.

Question 1: When using the on-board clock as the sample clock on the PXI-6561/2, is it possible to enable and disable the clock dynamically during operation? I.e. can the clock be turned off and on while the board is configured?

Question 2: I have read that the data lines may be skewed with respect to the sample clock. Is it possible to skew one data line and not skew the others?
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Message 1 of 7
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Hi mlloyd,

For your data delay question, every line can be individually configured for one of three settings: rising edge of sample clock, falling edge of sample clock, or delay from rising edge. Every channel that uses the "delay" setting must be configured for the same delay. For example,

Channel 0 = rising edge
Channel 1 = falling edge
Channel 2 = 15% of clock cycle
Channel 3 = 15% of clock cycle
Channel 4 = rising edge

is allowed. You could not, however, change channel 3 to be 5% in the example above, because you would have two "delay" channels set to different delays.

The sample clock may be enabled or disabled while the board is configured, but the acquisition or generation may not be running at the time. You will need to stop the operation, disable or enable the clock, then restart the operation. Since you will not need to reinitialize and reconfigure the entire session, this sequence will happen quickly, but the data input or output will need to stop briefly.

I hope that helps,
Allen
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Allen,
You have been very helpful! Your answers made me think of a few more questions:

1. In order to stop data generation/acquisition, is there a handshaking procedure that is followed?

2. After transmission stops, do you know about how many clock cycles it would take if you were running the clock between 50MHz and 100MHz before you could disable the clock?

3. Can data still be sent with the sample clock disabled?

Thanks again for your assistance in this matter!

Regards,
mlloyd
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Message 3 of 7
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Hi mlloyd,

The procedure for stopping and starting an acquisition or generation session on an SMC-based digital board (656x, 655x, 654x) typically will involve a couple of software calls. Let's say that you have setup a continuous generation by setting the generation repeat mode to continuous. Once the generation is running, you will need to call the niHSDIO Abort function to stop the generation, and you will need to call the niHSDIO Initiate function to start the generation after you change the sample clock setting (discussed below). On the other hand, if you are performing a finite generation or acquisition, the session will stop automatically after the specified number of samples have been generated or acquired. In this case, you will not need to call the Abort function since the session is already stopped.

I want to make a distinction between starting and stopping the data versus starting and stopping the session. Using a pause trigger, you can actually stop the data, but the session itself is still running. It is the session that must be stopped before you can change your settings. Since this is done with software calls, I cannot say how many clock cycles will pass. The sequence of calls should take on the order of a few milliseconds, but that will depend on the speed of your system.

The setting that I think you will need in this case is whether to export the sample clock from the 6561. We have a shipping example that shows how to export the sample clock, but it is a simple matter of calling the niHSDIO Export Signal function. You specify that you want to export the sample clock, then choose which output pin. To stop exporting the clock, you would again call the Export Signal function, telling it to not export the sample clock. Internally, the sample clock is running regardless of whether it is exported. That's a long way of saying "yes", you can continue to send data while the sample clock is not exported.

Hope that helps,
Allen
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Allen,
Thanks for the level of detail in your response. It looks like it might work for our application to start and stop exporting the sample clock, especially since we'll only be dealing with finite data transfers/acquisitions. I guess now it's a question of whether or not it matters that the clock will be exported a few milliseconds longer than the data generation...

Thanks for your help!
Regards,
mlloyd
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Another quick question: do you know where I can find more details on the events generated from the NI 6561? Specifically, what is the handshaking protocol on the PFI channels?

Thanks!
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Message 6 of 7
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Hi mlloyd,

You can find information about the events in the Help file, which installs with the HSDIO driver, or can be found here: http://digital.ni.com/manuals.nsf/websearch/49940593A32A192486256F8E00577F66

Go to Devices --> NI 656X --> Generation --> Dynamic Generation --> Triggers and Events.

There isn't exactly a handshaking protocol associated with the PFI lines, but perhaps the event descriptions will tell you what you need. Please see the 656X specifications (http://digital.ni.com/manuals.nsf/websearch/6B85302D4AD78B1986256F8100707620) for information about any delays that are associated with the triggers and/or events.

Allen
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