sync digital input/output with falling/rising edge with 6534

[Scheffe]

Hello,

could someone tell me, if it is possible to:

* send at one line a digital signal with rising edge
* recieve at one line a digital signal with falling edge

also should be sent

* the clk to sync with the external device

best regards
Newbie Scheffe

[Michael Sallaberger]

Hello,

please post your question more detailed:

-what software and what hardware do you use?
-what is the purpose of your task?
-.....

Regards
Michael Sallaberger
NI-Support

[Scheffe]

Okay, I'm working with the PXI 6534 and Labview 7.1.

My goal is, to realize SPI-Communication over this PXI. Therefore I need the card configured as followed:

* 1 Line as Chip Select signal
* 1 Line providing my Clock Signal (10MHZ)
* 1 Line sending data at rising edge (see above)
* 1 Line receiving dat at falling edge

at ever rising/falling edge i just have to transmit/receive one bit.

Now the question:

a) I have to use pattern I/O, so how do I get the Clock signal at a line ? (In the Manual is written that in pattern Mode PCLK is not availible)

b) How do I relize triggering to this edges ?

Merci
Scheffe

[Sebastian N]

Dear Sheffe,

I have take an example VI. I have develop some features but I have not tested these with a PXI 6534 board. When an error occurs, if you start the VI. Please try some settings. A another way to realize your application is to use an AI triggered example VI, test it. When it works fine, take a AO example VI. When both VI's works without any errors try to connect both in one additional VI.
Hope this example and information help you to create your application.

SebastianN
NI Germany

[Scheffe]

Hello Sebastian,

thx for your help! But there is just this small problem left... I can't open your VI. Labview 7.1 tells me:

"Die Datei Multi-Function-Sync... ist kein VI"

could you please check, if there has been an error occured during uploading this file, or post it new, please.

best regards

Scheffe

[Sebastian N]

Hello Scheffe,


here I post the VI again. I have open the Vi before I post it. It works fine.
Hope that you can open it without problems.

Best regards.

SebastianN
NI Germany

[Allen H]

Hello Scheffe,

First, you are correct that PCLK is not available when in Pattern mode. Instead, you should use either REQ1 or REQ2 depending on which timing group you are using.

Take a look at the "Buffered Pattern Input.vi" and "Buffered Pattern Output.vi" shipping examples. You can find them in the example finder. From LabVIEW, select Help --> Find Examples. Then select Hardware Input and Output --> Traditional DAQ --> Digital Input and Output --> 653x.

Those examples will show you how to choose between rising edge and falling edge for your sample clock.

I hope that helps.

[Sebastian N]

Dear Scheffe,

here the VI again.

Hope you can open the VI. I have made a test and it works fine.

Best Regards.

SebastianN

NI Germany

[Scheffe]

Okay, thx to all of you for your help ! Now it's running.

But at the end I have to say, that the example of the Multifunction AI/AO is not so useful, because with the PXI 6534 you can't use the DAQ VIs. The best example for was this Link

http://sine.ni.com/apps/we/niepd_web_display.display_epd4?p_guid=B45EACE3D87356A4E034080020E74861&p_node=DZ52321&p_source=External

you just have to config it for pattern I/O. So you use the generated REQ1 signal over the RTSI-Bus to supply REQ2...

Best regards and thx again

Scheffe