I have been doing some performance measurements on the code needed for a) writing samples to the DA FIFO and b) reading data from the AD FIFO on a 6259 board using the DDK samples and the VISA package.
The code in case a) is just a loop including sample conversion and register write. I case b) it is a check empty flag - read register - convert sample loop. In my application I need 16 input channels at 40 kS/s and 4 output channels at 40 kS/s. The data will be processed in chunks of 40 samples/channel every 1 ms.
The results are:
a) Writing 20 samples to the DA FIFO takes ~3.2 us = ~0.16 us/sample
b) Reading 100 samples from the AD FIFO (including check of FIFO empty flag) takes ~320 us = ~3.2 us/sample.
The results indicates that a register read takes approx. 10 times longer than a register write. Since I will be reading 640 samples and writing 160 samples every 1 ms in my application, this isn't fast enough.
My questions are:
Is the read access to the board registers really this slow compared to writes or is there some wait-state settings that need some tweeking?
Whould I gain any performance using DMA?
The tests are performed on a Intel Xeon 3.8GHz machine.
